MC68HC711K4CFN4 Freescale Semiconductor, MC68HC711K4CFN4 Datasheet - Page 23

• Manufacturer Part Number: MC68HC711K4CFN4
• Description: IC MCU 24K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711K4CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

M68HC11K Family
MOTOROLA
Technical Data — M68HC11K Family
Table
1-1
2-1
2-2
3-1
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10 XOUT Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
5-1
5-2
5-3
5-4
5-5
5-6
5-7
6-1
Freescale Semiconductor, Inc.
For More Information On This Product,
M68HC11K Family Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I/O Ports and Peripheral Functions. . . . . . . . . . . . . . . . . . . . . . 42
Port Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Registers with Limited Write Access. . . . . . . . . . . . . . . . . . . . . 76
Synchronization Character Selection . . . . . . . . . . . . . . . . . . . . 79
Hardware Mode Select Summary. . . . . . . . . . . . . . . . . . . . . . . 80
Default Memory Map Addresses . . . . . . . . . . . . . . . . . . . . . . . 83
RAM Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Scope of EEPROM Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
EEPROM Block Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Reset Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
COP Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
IRVNE Operation After Reset . . . . . . . . . . . . . . . . . . . . . . . . . 113
XOUT Clock Divide Select . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Interrupt and Reset Vector Assignments . . . . . . . . . . . . . . . . 118
Stacking Order on Entry to Interrupts . . . . . . . . . . . . . . . . . . .119
Highest Priority Interrupt Selection . . . . . . . . . . . . . . . . . . . . . 124
Port Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
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