MC68HC711K4CFN4 Freescale Semiconductor, MC68HC711K4CFN4 Datasheet - Page 51

• Manufacturer Part Number: MC68HC711K4CFN4
• Description: IC MCU 24K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711K4CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.3.6.4 Negative (N)
3.3.6.5 Interrupt Mask (I)
3.3.6.6 Half Carry (H)
M68HC11K Family
MOTOROLA
NOTE:
an internal implied subtraction and the condition codes, including Z,
reflect the results of that subtraction. A few operations (INX, DEX, INY,
and DEY) affect the Z bit and no other condition flags.
The N bit is set if the result of an arithmetic, logic, or data manipulation
operation is negative, meaning that the most significant bit (MSB) of the
result is a 1. Otherwise, the N bit is cleared. To determine quickly if the
MSB of a particular byte is set, load it into an accumulator and then
check the status of the N bit.
When the interrupt mask bit is set, it disables all maskable interrupt
requests (IRQs). The CPU continues to operate uninterrupted while
interrupts remain pending until the I bit is cleared. Every reset sets the
I bit by default and only a software instruction can clear it. When the
processor recognizes an interrupt, it stacks the registers, sets the I bit,
and then fetches the interrupt vector. The final instruction of an interrupt
service routine is usually a return from interrupt (RTI), which restores the
registers to the values that were present before the interrupt occurred
and clears the I bit.
Although the I bit can be cleared earlier in the interrupt service routine,
avoid nesting interrupts in this way without a clear understanding of
latency and of the arbitration mechanism.
Refer to
The H bit is set when a carry occurs between bits 3 and 4 of the
arithmetic logic unit during an ADD, ABA, or ADC instruction. Otherwise,
the H bit is cleared. Half carry is used during binary-coded decimal
(BCD) operations.
Freescale Semiconductor, Inc.
For More Information On This Product,
Section 5. Resets and
Central Processor Unit (CPU)
Go to: www.freescale.com
Interrupts.
Central Processor Unit (CPU)
CPU Registers
Technical Data
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