MC68HC711P2CFN4

Manufacturer Part NumberMC68HC711P2CFN4
DescriptionIC MCU 32K OTP 4MHZ 84-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711P2CFN4 datasheet
 


Specifications of MC68HC711P2CFN4

Core ProcessorHC11Core Size8-Bit
Speed4MHzConnectivityMI Bus, SCI, SPI
PeripheralsPOR, PWM, WDTNumber Of I /o50
Program Memory Size32KB (32K x 8)Program Memory TypeOTP
Eeprom Size640 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case84-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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Freescale Semiconductor, Inc.
MC68HC11P2
MC68HC711P2
Technical Data
M68HC11
Microcontrollers
MC68HC11P2/D
Rev. 1, 4/2002
For More Information On This Product,
Go to: www.freescale.com

MC68HC711P2CFN4 Summary of contents

  • Page 1

    ... Freescale Semiconductor, Inc. M68HC11 Microcontrollers For More Information On This Product, Go to: www.freescale.com MC68HC11P2 MC68HC711P2 Technical Data MC68HC11P2/D Rev. 1, 4/2002 ...

  • Page 2

    ... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

  • Page 3

    ... Freescale Semiconductor, Inc. MC68HC11P2 MC68HC711P2 Technical Data — Rev 1.0 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any ...

  • Page 4

    ... Freescale Semiconductor, Inc. Technical Data For More Information On This Product, Go to: www.freescale.com MC68HC11P2 — Rev 1.0 ...

  • Page 5

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC11P2 List of Paragraphs Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Section 1. General Description . . . . . . . . . . . . . . . . . . . . 17 Section 2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . 21 Section 3. Operating Modes and On-Chip Memory . . . . 41 Section 4. Parallel Input/Output . . . . . . . . . . . . . . . . . . . . 73 Section 5. Serial Communications Interface (SCI Section 6. Motorola Interconnect Bus (MI BUS 109 Section 7 ...

  • Page 6

    ... Freescale Semiconductor, Inc. List of Paragraphs Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Technical Data For More Information On This Product, List of Paragraphs Go to: www.freescale.com MC68HC11P2 — Rev 1.0 ...

  • Page 7

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC11P2 1.1 1.2 1.3 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 MC68HC11P2 — Rev 1.0 For More Information On This Product, List of Paragraphs Table of Contents List of Figures List of Tables Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Features ...

  • Page 8

    ... Freescale Semiconductor, Inc. Table of Contents 2.11 2.12 2.13 Section 3. Operating Modes and On-Chip Memory 3.1 3.2 3.3 3.4 3.5 3.6 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 Technical Data For More Information On This Product, VRH and VRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PG7/R/W ...

  • Page 9

    ... Freescale Semiconductor, Inc. Section 5. Serial Communications Interface (SCI) 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 MC68HC11P2 — Rev 1.0 For More Information On This Product, Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Transmit operation ...

  • Page 10

    ... Freescale Semiconductor, Inc. Table of Contents 7.1 7.2 7.3 7.4 7.5 7.6 7.7 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9.1 9.2 9.3 9.4 Technical Data For More Information On This Product, Section 7. Serial Peripheral Interface (SPI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Functional description ...

  • Page 11

    ... Freescale Semiconductor, Inc. 9.7 10.1 10.2 10.3 10.4 10.5 10.6 10.7 11.1 11.2 11.3 11.4 11.5 11.6 11.7 12.1 12.2 12.3 12.4 12.5 MC68HC11P2 — Rev 1.0 For More Information On This Product, Operation in STOP and WAIT modes 184 Section 10. Resets and Interrupts Contents ...

  • Page 12

    ... Freescale Semiconductor, Inc. Table of Contents 12.7 13.1 13.2 13.3 14.1 14.2 15.1 15.2 15.3 15.4 Technical Data For More Information On This Product, Control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Section 13. Mechanical Data Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Package dimensions 249 Section 14. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Introduction ...

  • Page 13

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC11P2 Figure 1-1 2-1 2-2 2-3 2-4 2-5 3-1 3-2 5-1 5-2 5-3 6-1 6-2 6-3 6-4 7-1 7-2 8-1 8-2 8-3 8-4 8-5 9-1 9-2 9-3 10-1 Processing flow out of reset ( 206 MC68HC11P2 — Rev 1.0 ...

  • Page 14

    ... Freescale Semiconductor, Inc. List of Figures 10-4 Interrupt priority resolution ( 209 10-5 Interrupt priority resolution ( 210 10-6 Interrupt source resolution within the SCI subsystem 211 11-1 Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 11-2 Stacking operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12-1 Test methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 12-2 Timer inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 12-3 Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 12-4 Interrupt timing ...

  • Page 15

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC11P2 Table 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 4-1 5-1 7-1 8-1 8-2 8-3 8-4 9-1 10-1 COP timer rate select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 10-2 Reset cause, reset vector and operating mode . . . . . . . . . . . 192 10-3 Highest priority interrupt selection . . . . . . . . . . . . . . . . . . . . . 198 10-4 Interrupt and reset vector assignments ...

  • Page 16

    ... Freescale Semiconductor, Inc. List of Tables Technical Data For More Information On This Product, List of Tables Go to: www.freescale.com MC68HC11P2 — Rev 1.0 ...

  • Page 17

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC11P2 1.1 Contents 1.2 1.3 1.2 Introduction The MC68HC11P2 8-bit microcomputer is a member of the M68HC11 family of HCMOS microcomputers. In addition to 32kbytes of ROM, the MC68HC11P2 contains 1kbyte of RAM and 640 bytes of EEPROM. With its advanced timer and communication features (including MI BUS the MC68HC11P2 is especially suitable for mobile communications and automotive applications ...

  • Page 18

    ... Freescale Semiconductor, Inc. General Description 1.3 Features • • • • • • • • • • • • • Technical Data For More Information On This Product, Low power, high performance M68HC11 CPU core, with 4MHz bus capability Power saving PLL clock circuit, with automatic disable during WAIT mode 32kbytes of User ROM (MC68HC11P2) ...

  • Page 19

    ... Freescale Semiconductor, Inc. ROM or EPROM (including 64 bytes for vectors) 640 bytes EEPROM 1024 bytes RAM VPPE/XIRQ Interrupts IRQ & RESET mode LIR/MODA select VSTBY/MODB XTAL EXTAL Oscillator E XFC PLL VDDSYN 5 VDD VSS 5 MC68HC11P2 — Rev 1.0 For More Information On This Product, ...

  • Page 20

    ... Freescale Semiconductor, Inc. General Description Technical Data For More Information On This Product, General Description Go to: www.freescale.com MC68HC11P2 — Rev 1.0 ...

  • Page 21

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC11P2 2.1 Contents 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.2 Introduction The MC68HC11P2 is available in an 84-pin plastic-leaded chip carrier (PLCC); the MC68HC711P2 is also available in an 84-pin windowed cerquad package, to allow full use of the EPROM. Most pins on this MCU serve two or more functions, as described in the following paragraphs ...

  • Page 22

    ... Freescale Semiconductor, Inc. Pin Descriptions MODB/VSTBY 2.3 VDD and VSS Power is supplied to the microcontroller via these pins. VDD is the positive supply and VSS is ground. The MCU operates from a single 5V (nominal) power supply the nature of CMOS designs that very fast signal transitions occur on the MCU pins ...

  • Page 23

    ... Freescale Semiconductor, Inc. Bypassing requirements vary, depending on how heavily the MCU pins are loaded. The MC68HC11P2 MCU has five VDD pins and five VSS pins. One pair of these pins is reserved for supplying power to the analog-to-digital converter (VDD AD, VSS AD); two pairs are used for the internal logic (VDD, VSS) ...

  • Page 24

    ... Freescale Semiconductor, Inc. Pin Descriptions 2.5 Crystal driver and external clock input (XTAL, EXTAL) These two pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. The frequency applied to these pins must be four times higher than the desired E clock rate (unless the PLL circuit is used to provide the E clock) ...

  • Page 25

    ... Freescale Semiconductor, Inc. In all cases, use caution when designing circuitry associated with the oscillator pins. Load capacitances shown in the oscillator circuits include all stray layout capacitances. See (a) Common crystal connections (b) External oscillator M68HC11 connections EXTAL M68HC11 10 M¾ XTAL (c) One crystal driving two MCUs Figure 2-3. Oscillator connections MC68HC11P2 — ...

  • Page 26

    ... Freescale Semiconductor, Inc. Pin Descriptions 2.6 E clock output ( the output connection for the internally generated E clock. The signal from E is used as a timing reference. The frequency of the E clock output is one quarter that of the input frequency at the XTAL and EXTAL pins (except when the PLL is used as the clock source). When E clock output is low, an internal process is taking place ...

  • Page 27

    ... Freescale Semiconductor, Inc. The PLL filter has two bandwidths that are automatically selected by the PLL, if the AUTO bit in PLLCR is set. Whenever the PLL is first enabled, the wide bandwidth mode is used. This enables the PLL frequency to ramp up quickly. When the output frequency is near the desired value, the filter is switched to the narrow bandwidth mode, to make the final frequency more stable ...

  • Page 28

    ... Freescale Semiconductor, Inc. Pin Descriptions 2.7.2 Changing the PLL frequency To change the PLL frequency it is necessary to perform the following sequence of events, in order to prevent possible bursts of high frequency operation during the reconfiguration of the PLL: 1. Switch to the low frequency bus rate (BCS = 0) 2. Disable the PLL (PLLON = 0) 3 ...

  • Page 29

    ... Freescale Semiconductor, Inc. This bit activates the synthesizer circuit without connecting it to the control circuit. This allows the circuit to stabilize before it drives the CPU clocks. PLLON is set by reset, to allow the control loop to stabilize during power up. PLLON cannot be cleared whilst using VCOOUT to drive the internal processor clock, i.e. when BCS is set. BCS — ...

  • Page 30

    ... Freescale Semiconductor, Inc. Pin Descriptions the PLL is near the specified frequency. The high bandwidth driver is then disabled and BWC is cleared by internal circuitry. Reset clears this bit. VCOT — VCO test (Test mode only Loop filter operates as specified by AUTO and BWC Low bandwidth mode of the PLL filter is disabled. ...

  • Page 31

    ... Freescale Semiconductor, Inc. Any interrupt, any reset, or the assertion of RAF in any of the SCIs will allow the PLL to resume operating at the frequency specified in the SYNR. The user must set BCS after the PLL has had time to adjust (t PLLS become set, hence the PLL will not resume normal operation. ...

  • Page 32

    ... Freescale Semiconductor, Inc. Pin Descriptions 2.8 Interrupt request (IRQ) The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge sensitive triggering or level sensitive triggering is program selectable (OPTION register). IRQ is always configured to level sensitive triggering at reset. NOTE: Connect an external pull-up resistor, typically 4.7 k¾ used in a level sensitive wired-OR configuration ...

  • Page 33

    ... Freescale Semiconductor, Inc. 2.10 MODA and MODB (MODA/LIR and MODB/VSTBY) During reset, MODA and MODB select one of the four operating modes. Refer to After the operating mode has been selected, the LIR pin provides an open-drain output to indicate that execution of an instruction has begun. ...

  • Page 34

    ... Freescale Semiconductor, Inc. Pin Descriptions 2.11 VRH and VRL These pins provide the reference voltages for the analog-to-digital converter. 2.12 PG7/R/W This pin provides two separate functions, depending on the operating mode. In single chip and bootstrap modes, PG7/R/W acts as input/output port G bit 7. Refer to information ...

  • Page 35

    ... Freescale Semiconductor, Inc. 2.13.1 Port A Port 8-bit general-purpose I/O port with a data register (PORTA) and a data direction register (DDRA). Port A pins share functions with the 16-bit timer system (see PORTA can be read at any time: inputs return the pin level; outputs MC68HC11P2 — Rev 1.0 For More Information On This Product, Table 2-1 ...

  • Page 36

    ... Freescale Semiconductor, Inc. Pin Descriptions outputs. Writes to PORTA do not change the pin state when the pins are configured for timer output compares. Out of reset, port A pins [7:0] are general-purpose high-impedance inputs. When the functions associated with these pins are disabled, the bits in DDRA govern the I/O state of the associated pin ...

  • Page 37

    ... Freescale Semiconductor, Inc. The CWOM control bit in the OPT2 register disables port C’s P-channel output drivers. Because the N-channel driver is not affected by CWOM, setting CWOM causes port C to become an open-drain-type output port suitable for wired-OR operation. In wired-OR mode (PORTC bits at logic level zero), the pins are actively driven low by the N-channel driver ...

  • Page 38

    ... Freescale Semiconductor, Inc. Pin Descriptions 2.13.6 Port F Port 8-bit general-purpose I/O port with a data register (PORTF) and a data direction register (DDRF). In single chip mode, port F pins are general-purpose I/O pins (PF[7:0]). In expanded mode, port F pins act as the low-order address lines (A[7:0]) of the address bus. ...

  • Page 39

    ... Freescale Semiconductor, Inc. PORTH can be read at any time: inputs return the pin level; outputs return the pin driver input level. If PORTH is written, the data is stored in internal latches. The pins are driven only if they are configured as outputs in single chip or bootstrap mode. Port H pins include on-chip pull-up or pull-down devices that can be enabled or disabled via the Port pull-up assignment register (PPAR). Port H [7:4] have pull-up resistors ...

  • Page 40

    ... Freescale Semiconductor, Inc. Pin Descriptions Technical Data For More Information On This Product, Pin Descriptions Go to: www.freescale.com MC68HC11P2 — Rev 1.0 ...

  • Page 41

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC11P2 Section 3. Operating Modes and On-Chip Memory 3.1 Contents 3.2 3.3 3.4 3.5 3.6 3.2 Introduction This section contains information about the modes that define MC68HC11P2 operating conditions, and about the on-chip memory that allows the MCU to be configured for various applications. ...

  • Page 42

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory 3.3.1 Single chip operating mode In single chip operating mode, the MC68HC11P2 microcontroller has no external address or data bus. Ports and the R/W pin are available for general-purpose parallel I/O. 3.3.2 Expanded operating mode In expanded operating mode, the MCU can access a 64kbyte physical address space ...

  • Page 43

    ... Freescale Semiconductor, Inc. 3.3.4 Special bootstrap mode When the MCU is reset in special bootstrap mode, a small on-chip ROM is enabled at address $BE40–$BFFF. The ROM contains a reset vector and a bootloader program. The MCU fetches the reset vector, then executes the bootloader. For normal use of the bootloader program, send a synchronization byte $FF to the SCI receiver at either E clock ÷ ...

  • Page 44

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory 3.4 On-chip memory The MC68HC11P2 MCU includes 1024 bytes of on-chip RAM, 32kbytes of ROM/EPROM and 640 bytes of EEPROM. The bootloader ROM occupies a 512 byte block of the memory map. The CONFIG register is implemented as a separate EEPROM byte. ...

  • Page 45

    ... Freescale Semiconductor, Inc. registers are both mapped to the same 4k boundary, RAM starts at $x080 and 128 bytes are remapped at $x400–$x47F. Otherwise, RAM starts at $x000. Remapping is accomplished by writing appropriate values into the two nibbles of the INIT register. The 640-byte EEPROM is initially located at $0D80 after reset when EEPROM is enabled in the memory map by the CONFIG register ...

  • Page 46

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory The on-chip RAM is a fully static memory. RAM contents can be preserved during periods of processor inactivity by either of two methods, both of which reduce power consumption: 1. During the software-based STOP mode, MCU clocks are stopped reduce power consumption to a minimum ...

  • Page 47

    ... Freescale Semiconductor, Inc. 3.4.2 Registers In Table shown in ascending order within the 128-byte register block. The addresses shown are for default block mapping ($0000–$007F), however, the INIT register remaps the block to any 4k page ($x000–$x07F). Table 3-2. Register and control bit assignments (Sheet ...

  • Page 48

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory Table 3-2. Register and control bit assignments (Sheet Register name Address Timer output compare 4 (TOC4) high $001C (bit 15) Timer output compare 4 (TOC4) low $001D Capture 4/compare 5 (TI4/O5) high $001E Capture 4/compare 5 (TI4/O5) low ...

  • Page 49

    ... Freescale Semiconductor, Inc. Table 3-2. Register and control bit assignments (Sheet Register name Address reserved $0040 reserved $0041 reserved $0042 reserved $0043 reserved $0044 reserved $0045 reserved $0046 reserved $0047 reserved $0048 reserved $0049 reserved $004A reserved $004B reserved $004C reserved ...

  • Page 50

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory Table 3-2. Register and control bit assignments (Sheet Register name Address Pulse width count 2 (PWCNT2) $0065 Pulse width count 3 (PWCNT3) $0066 Pulse width count 4 (PWCNT4) $0067 Pulse width period 1 (PWPER1) $0068 Pulse width period 2 (PWPER2) ...

  • Page 51

    ... Freescale Semiconductor, Inc. 3.5 System initialization Registers and bits that control initialization and the basic operation of the MCU are protected against writes except under special circumstances. The following table lists registers that can be written only once after reset, or that must be written within the first 64 cycles after reset. ...

  • Page 52

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory stand-by power input (VSTBY), which allows the RAM contents to be maintained in the absence of V Refer to control bits and the four operating modes. A normal mode is selected when MODB is logic one during reset. One of three reset vectors is fetched from address $FFFA–$FFFF, and program execution begins from the address indicated by this vector ...

  • Page 53

    ... Freescale Semiconductor, Inc. PSEL[4:0] — Priority select bits (refer to 3.5.2 Initialization Because bits in the following registers control the basic configuration of the MCU, an accidental change of their values could cause serious system problems. The protection mechanism, overridden in special operating modes, requires a write to the protected bits only within the first 64 bus cycles after any reset, or only once after each reset ...

  • Page 54

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory These bits can be read at any time. The value read is the one latched into the register from the EEPROM cells during the last reset sequence. A new value programmed into this register is not readable until after a subsequent reset sequence ...

  • Page 55

    ... Freescale Semiconductor, Inc. 3.5.2.2 INIT — RAM and I/O mapping register Address bit 7 RAM & I/O mapping (INIT) $003D RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0 0000 0000 The internal registers used to control the operation of the MCU can be relocated on 4k boundaries within the memory space with the use of INIT ...

  • Page 56

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory NOTE: When the memory map has the 128-byte register block mapped at the same location as RAM, the registers have priority and the RAM is relocated to the memory space immediately following the register block. This mapping feature keeps all the RAM available for use. Refer to ...

  • Page 57

    ... Freescale Semiconductor, Inc. 3.5.2.3 INIT2 — EEPROM mapping and MI BUS delay register Address bit 7 EEPROM mapping (INIT2) $0037 This register determines the location of EEPROM in the memory map. INIT2 may be read at any time but bits 7–4 may be written only once after reset in normal modes (bits 3–0 may be written at any time). ...

  • Page 58

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory M3DL1, M3DL0, M2DL1, M2DL0 — MI BUS delay select (refer to Motorola Interconnect Bus (MI 3.5.2.4 OPTION — System configuration options register 1 Address bit 7 System config. options 1 $0039 ADPU CSEL IRQE (OPTION) The 8-bit special-purpose OPTION register sets internal system configuration options during initialization ...

  • Page 59

    ... Freescale Semiconductor, Inc. After enabling the A/D power, at least 100µs should be allowed for system stabilization. CSEL — Clock select (refer A/D and EEPROM use internal RC clock source (about 0 = A/D and EEPROM use system E clock (must be at least 1MHz). Selects alternate clock source for on-chip EEPROM and A/D charge pumps ...

  • Page 60

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory 3.5.2.5 OPT2 — System configuration options register 2 Address bit 7 System config. options 2 (OPT2) $0038 LIRDV CWOM LIRDV — LIR driven 1 = Enable LIR drive high pulse LIR only driven low (requires pull-up on pin). In single chip and bootstrap modes, this bit has no meaning or effect. ...

  • Page 61

    ... Freescale Semiconductor, Inc. In single chip modes this bit determines whether the E clock drives out from the chip pin is driven low clock is driven out from the chip. Refer to the following table for a summary of the operation immediately following reset. Mode Single chip Expanded ...

  • Page 62

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory BULKP — Bulk erase of EEPROM protect 1 = EEPROM cannot be bulk or row erased EEPROM can be bulk erased normally. Bit 6 — not implemented; always reads zero. BPRT4 — Block protect bit for top 128 bytes of EEPROM (see below) PTCON — ...

  • Page 63

    ... Freescale Semiconductor, Inc. 3.5.2.7 TMSK2 — Timer interrupt mask register 2 Address bit 7 Timer interrupt mask 2 (TMSK2) $0024 PR[1:0] are time-protected control bits and can be changed only once and then only within the first 64 bus cycles after reset in normal modes. NOTE: Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable the corresponding interrupt sources. TOI — ...

  • Page 64

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory 3.6 EPROM, EEPROM and CONFIG register 3.6.1 EPROM Using the on-chip EPROM programming feature requires an external power supply (V EPROG register. Program EPROM at room temperature only and place an opaque label over the quartz window after programming. ...

  • Page 65

    ... Freescale Semiconductor, Inc. EXCOL — Select extra columns 1 = User array disabled; extra column selected User array selected. The extra column may be accessed at bit 7; addresses use bits 11–5, bits 4–0 must be ones. The EXCOL bit always reads zero in normal modes and may be read or written only in special modes. ...

  • Page 66

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory utility can be used. To use the resident utility, bootload a three-byte program consisting of a single jump instruction to $BF00. $BF00 is the starting address of a resident EPROM programming utility. The utility program sets the X and Y index registers to default values, then receives programming data from an external host and puts it in EPROM ...

  • Page 67

    ... Freescale Semiconductor, Inc. 3.6.2.1 PPROG — EEPROM programming control register Address bit 7 EEPROM programming $003B (PPROG) NOTE: Writes to EEPROM addresses are inhibited while EEPGM is one. A write to a different EEPROM location is prevented while a program or erase operation is in progress. ODD — Program odd rows in half of EEPROM (Test) EVEN — ...

  • Page 68

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory EELAT — EEPROM latch control 1 = EEPROM address and data bus set up for programming EEPROM address and data bus set up for normal reads. When the EELAT bit is cleared, the EEPROM can be read were a ROM. The block protect register has no effect during reads. ...

  • Page 69

    ... Freescale Semiconductor, Inc. 6. Clear the PPROG register to reconfigure the EEPROM address The following is an example of how to bulk erase the 512-byte EEPROM. The CONFIG register is not affected in this example. BULKE 3.6.2.3 EEPROM row erase The following example shows how to perform a fast erase of large ...

  • Page 70

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory 3.6.3 CONFIG register programming Because the CONFIG register is implemented with EEPROM cells, use EEPROM procedures to erase and program this register. The procedure for programming is the same as for programming a byte in the EEPROM array, except that the CONFIG register address is used. CONFIG can be programmed or erased (including byte erase) while the MCU is operating in any mode, provided that PTCON in BPROT is clear ...

  • Page 71

    ... Freescale Semiconductor, Inc. 3.6.4 RAM and EEPROM security The optional security feature protects the contents of EEPROM and RAM from unauthorized access. A program key portion of a program, can be protected against duplication. To accomplish this, the protection mechanism restricts operation of protected devices to single chip modes, and thus prevents the memory locations from being monitored externally (single chip modes do not allow visibility of the internal address and data buses) ...

  • Page 72

    ... Freescale Semiconductor, Inc. Operating Modes and On-Chip Memory NOSEC — EEPROM security disabled 1 = Disable security Enable security. NOTE: MC68HC11P2 devices are normally manufactured with NOSEC set to one and the security option is unavailable. On special request, a mask option is selected during fabrication that enables the security mode. On these parts, the secure mode is invoked by programming the NOSEC bit to zero ...

  • Page 73

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC11P2 4.1 Contents 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.2 Introduction The MC68HC11P2 has input/output lines and 8 input-only lines, depending on the operating mode. To enhance the I/O functions, the data bus of this microcontroller is nonmultiplexed. The following table is a summary of the configuration and features of each port. MC68HC11P2 — ...

  • Page 74

    ... Freescale Semiconductor, Inc. Parallel Input/Output Port NOTE: Do not confuse pin function with the electrical state of that pin at reset. All general-purpose I/O pins that are configured as inputs at reset are in a high-impedance state and the contents of the port data registers are undefined; in port descriptions, a ‘u’ indicates this condition. The pin function is mode dependent ...

  • Page 75

    ... Freescale Semiconductor, Inc. 4.3.1 PORTA — Port A data register Address bit 7 Port A data (PORTA) $0000 This is a read/write register and is not affected by reset. The bits may be read and written at any time, but, when a pin is allocated to its alternate function, a write to the corresponding register bit has no affect on the pin state. 4.3.2 DDRA — ...

  • Page 76

    ... Freescale Semiconductor, Inc. Parallel Input/Output The state of the pins on reset is mode dependent. In single chip or bootstrap mode, port B pins are high-impedance inputs with selectable internal pull-up resistors (see expanded or test mode, port B pins are high order address outputs and PORTB/DDRB are not in the memory map. ...

  • Page 77

    ... Freescale Semiconductor, Inc. 4.5 Port C Port 8-bit bidirectional port, with both data and data direction registers. In addition to their I/O capability, port C pins are used as the nonmultiplexed data bus pins, as shown in the following table. The state of the pins on reset is mode dependent. In single chip or bootstrap mode, port C pins are high-impedance inputs ...

  • Page 78

    ... Freescale Semiconductor, Inc. Parallel Input/Output 4.5.2 DDRC — Data direction register for port C Address bit 7 Data direction C (DDRC) $0007 DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 0000 0000 DDC[7:0] — Data direction for port The corresponding pin is configured as an output. ...

  • Page 79

    ... Freescale Semiconductor, Inc. 4.6.2 DDRD — Data direction register for port D Address bit 7 Data direction D (DDRD) $0009 Bits [7:6] — Reserved; always read zero DDD[5:0] — Data direction for port The corresponding pin is configured as an output The corresponding pin is configured as an input. ...

  • Page 80

    ... Freescale Semiconductor, Inc. Parallel Input/Output 4.7.1 PORTE — Port E data register Address bit 7 Port E data (PORTE) $000A This is a read-only register and is not affected by reset. The bits may be read at any time. NOTE: As port E shares pins with the A/D converter, a read of the this register may affect any conversion currently in progress coincides with the sample portion of the conversion cycle ...

  • Page 81

    ... Freescale Semiconductor, Inc. 4.8.1 PORTF — Port F data register Address bit 7 Port F data (PORTF) $0005 The bits may be read and written at any time and are not affected by reset. 4.8.2 DDRF — Data direction register for port F Address bit 7 Data direction F (DDRF) $0003 DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 0000 0000 DDF[7:0] — ...

  • Page 82

    ... Freescale Semiconductor, Inc. Parallel Input/Output 4.9.1 PORTG — Port G data register Address bit 7 Port G data (PORTG) $007E The bits may be read and written at any time and are not affected by reset. 4.9.2 DDRG — Data direction register for port G Address bit 7 Data direction G (DDRG) $007F DDG7 DDG6 DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 0000 0000 DDG[7:0] — ...

  • Page 83

    ... Freescale Semiconductor, Inc. ups on pins 7–4 and pull-downs on pins 3–0 (see down 4.10.1 PORTH — Port H data register Address bit 7 Port H data (PORTH) $007C This is a read/write register and is not affected by reset. The bits may be read and written at any time, but, when a pin is allocated to its alternate function, a write to the corresponding register bit has no affect on the pin state ...

  • Page 84

    ... Freescale Semiconductor, Inc. Parallel Input/Output 4.11.1 PPAR — Port pull-up assignment register Address bit 7 Port pull-up assignment (PPAR) $002C Bits [7:4] — Not implemented; always read zero xPPUE — Port x pin pull-up enable These bits control the on-chip pull-up devices connected to all the pins on I/O ports and H ...

  • Page 85

    ... Freescale Semiconductor, Inc. CWOM — Port C wired-OR mode 1 = Port C outputs are open-drain Port C operates normally. STRCH — Stretch external accesses (refer to On-Chip 1 = Off-chip accesses are extended by one E clock cycle Normal operation. IRVNE — Internal read visibility/not E (refer to On-Chip 1 = Data from internal reads is driven out of the external data bus. ...

  • Page 86

    ... Freescale Semiconductor, Inc. Parallel Input/Output PAREN — Pull-up assignment register enable 1 = PPAR register enabled; pull-ups can be enabled using PPAR PPAR register disabled; all pull-ups disabled. NOSEC — EEPROM security disabled (refer to On-Chip 1 = Disable security Enable security. NOCOP — COP system disable (refer COP system disabled ...

  • Page 87

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC11P2 Section 5. Serial Communications Interface (SCI) 5.1 Contents 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.2 Introduction The serial communications interface (SCI universal asynchronous receiver transmitter (UART). It has a non-return to zero (NRZ) format (one start, eight or nine data, and one stop bit) that is compatible with standard RS-232 systems ...

  • Page 88

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) The SCI shares I/O with two of port D’s pins: The SCI transmit and receive functions are enabled by TE and RE respectively, in SCCR2. The SCI features enabled on this MCU include: 13-bit modulus prescaler; idle line detect; receiver-active flag; transmitter and receiver hardware parity ...

  • Page 89

    ... Freescale Semiconductor, Inc. • • Selection of the word length is controlled by the M bit of SCCR1. 5.4 Transmit operation The SCI transmitter includes a parallel data register (SCDRH/SCDRL) and a serial shift register. The contents of the shift register can only be written through the serial data registers. This double buffered operation allows a character to be shifted out serially while another character is waiting in the serial data registers to be transferred into the shift register ...

  • Page 90

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) LOOPS WOMS † M WAKE ILT PE PT TIE TCIE RIE ILIE TE RE RWU SBK Technical Data For More Information On This Product, T8 Transmit buffer 10/11-bit TX shift register LOOPS M PE Transmitter PT control TE SBK Flag control WAKE PE PT ...

  • Page 91

    ... Freescale Semiconductor, Inc. 5.6 Wakeup feature The wakeup feature reduces SCI service overhead in multiple receiver systems. Software for each receiver evaluates the first character or frame of each message. All receivers are placed in wakeup mode by writing a one to the RWU bit in the SCCR2 register. When RWU is set, the receiver-related status flags (RDRF, IDLE, OR, NF, FE, and PF) are inhibited (cannot be set) ...

  • Page 92

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) receiver wakeup requires a minimum of one idle frame time between messages, and no idle time between frames within a message. 5.6.2 Address-mark wakeup Setting the WAKE bit in SCCR1 register enables address-mark wakeup mode. The address-mark wakeup method uses the MSB of each frame to differentiate between address information (MSB = 1) and actual message data (MSB = 0) ...

  • Page 93

    ... Freescale Semiconductor, Inc. The OR is cleared when the SCSR is read (with OR set), followed by a read of the SCI data registers. The noise flag (NF) bit is set if there is noise on any of the received bits, including the start and stop bits. The NF bit is not set until the RDRF flag is set ...

  • Page 94

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 5.8.1 SCBDH, SCBDL — SCI baud rate control registers Address bit 7 SCI 1 baud rate high (SCBDH) $0070 BTST BSPL SCI 1 baud rate low (SCBDL) $0071 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0000 0100 The contents of this register determine the baud rate of the SCI. BTST — ...

  • Page 95

    ... Freescale Semiconductor, Inc. 5.8.2 SCCR1 — SCI control register 1 Address bit 7 SCI 1 control 1 (SCCR1) $0072 The SCCR1 register provides the control bits that determine word length and select the method used for the wakeup feature. LOOPS — SCI loop mode enable 1 = SCI transmit and receive are disconnected from TXD and RXD 0 = SCI transmit and receive operate normally ...

  • Page 96

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) M — Mode (select character format Start bit, 9 data bits, 1 stop bit Start bit, 8 data bits, 1 stop bit. WAKE — Wakeup by address mark/idle 1 = Wakeup by address mark (most significant data bit set Wakeup by IDLE line recognition. ...

  • Page 97

    ... Freescale Semiconductor, Inc. 5.8.3 SCCR2 — SCI control register 2 Address bit 7 SCI 1 control 2 (SCCR2) $0073 The SCCR2 register provides the control bits that enable or disable individual SCI functions. TIE — Transmit interrupt enable 1 = SCI interrupt requested when TDRE status flag is set. ...

  • Page 98

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 5.8.4 SCSR1 — SCI status register 1 Address bit 7 SCI 1 status 1 (SCSR1) $0074 TDRE The bits in SCSR1 indicate certain conditions in the SCI hardware and are automatically cleared by special acknowledge sequences. TDRE — Transmit data register empty flag 1 = SCDR empty ...

  • Page 99

    ... Freescale Semiconductor, Inc. OR — Overrun error flag 1 = Overrun detected overrun set if a new character is received before a previously received character is read from SCDR. Clear the OR flag by reading SCSR1 with OR set and then reading SCDR. NF — Noise error flag 1 = Noise detected Unanimous decision. ...

  • Page 100

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 5.8.5 SCSR2 — SCI status register 2 Address bit 7 SCI 1 status 2 (SCSR2) $0075 In the SCSR2 only bit 0 is used, to indicate receiver active. The other seven bits always read zero. Bits [7:1] — Not implemented; always read zero RAF — ...

  • Page 101

    ... Freescale Semiconductor, Inc. 5.9 Status flags and interrupts The SCI transmitter has two status flags. These status flags can be read by software (polled) to tell when certain conditions exist. Alternatively, a local interrupt enable bit can be set to enable each of these status conditions to generate interrupt requests. Status flags are automatically set by hardware logic conditions, but must be cleared by software ...

  • Page 102

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 5.9.1 Receiver flags The SCI receiver has seven status flags, three of which can generate interrupt requests. The status flags are set by the SCI logic in response to specific conditions in the receiver. These flags can be read (polled) at any time by software ...

  • Page 103

    ... Freescale Semiconductor, Inc. Begin Yes RDRF = 1? No Yes Yes TDRE = 1? No Yes Yes IDLE = valid SCI interrupt request Figure 5-3. Interrupt source resolution within SCI MC68HC11P2 — Rev 1.0 For More Information On This Product, Note: The bit names shown are for SCI1. The ...

  • Page 104

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 5.10 Additional SCI subsystems In addition to the subsystem described in the above paragraphs (SCI1), the MC68HC11P2 has two other, similar, SCI modules (SCI2, SCI3). These two systems are identical to that described, with the following exceptions: SCI2 and SCI3 share I/O with four port H pins: The SCI2 transmit and receive functions are enabled by TE2 and RE2 respectively, in S2CR2 ...

  • Page 105

    ... Freescale Semiconductor, Inc. 5.10.1.1 S2BDH, S2BDL — SCI2/3 baud rate control registers Address bit 7 SCI/MI 2/3 baud high (S2BDH) $0050 B2TST B2SPL SCI/MI 2/3 baud low (S2BDL) $0051 The contents of this register determine the baud rate for both SCI2 and SCI3. For details of the bits and the corresponding baud rates see SCBDH, SCBDL — ...

  • Page 106

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 5.10.1.4 S2SR1 — SCI2 status register 1 Address bit 7 SCI/MI 2 status 1 (S2SR1) $0054 TDRE2 TC2 RDRF2 IDLE2 OR2 The bits in S2SR1 indicate certain conditions in the SCI hardware and are automatically cleared by special acknowledge sequences. For details of the bits, see 5.10.1.5 S2SR2 — ...

  • Page 107

    ... Freescale Semiconductor, Inc. 5.10.2.1 S3CR1 — SCI3 control register 1 Address bit 7 SCI/MI 3 control 1 (S3CR1) $005A LOPS3 WOMS3 MIE3 The S3CR1 register provides the control bits that determine word length and select the method used for the wakeup feature. Bit 5 has an MI BUS control function detailed below (for details of the other bits see — ...

  • Page 108

    ... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 5.10.2.4 S3SR2 — SCI3 status register 2 Address bit 7 SCI/MI 3 status 2 (S3SR2) $005D In S3SR2 only bit 0 is used, to indicate receiver active (see SCI status register 2 5.10.2.5 S3DRH, S3DRL — SCI3 data high/low registers Address bit 7 ...

  • Page 109

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC11P2 Section 6. Motorola Interconnect Bus (MI BUS) 6.1 Contents 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.2 Introduction The Motorola Interconnect Bus (MI BUS serial communications protocol which supports distributed real-time control efficiently and with a high degree of noise immunity typical bit rate for the data transfer of 20kHz ...

  • Page 110

    ... Freescale Semiconductor, Inc. Motorola Interconnect Bus (MI BUS) The MC68HC11P2 contains two similar MI BUS modules. For ease of reference, a full description of MI BUS2 is given, followed by a summary of MI BUS3, detailing its differences. The MI BUS uses a push-pull sequence to transfer data. The master device, which, in this case, is the MC68HC11P2, sends a push field to the slave devices connected to the bus ...

  • Page 111

    ... Freescale Semiconductor, Inc. 6.3 Push-pull sequence Communication between the MCU and the slave device always utilizes the same frame organization. First, the MCU sends serial data to the selected device. This data field is called the ‘push field’. At the end of the push field, the selected device automatically sends back to the MCU the data held during the push sequence. The MCU reads the serial data sent by the selected device. This data is called the ‘ ...

  • Page 112

    ... Freescale Semiconductor, Inc. Motorola Interconnect Bus (MI BUS) 6.4 The push field The push field consists of a start bit, a push synchronization bit, a push data field and a push address field. The start consists of three time slots having the dominant logical state ‘0’. The start marks the beginning of the message frame by violation of the rule of the Manchester code. The push synchronization bit consists of a biphase coded ‘ ...

  • Page 113

    ... Freescale Semiconductor, Inc. 6.6 Biphase coding Manchester biphase L coding is used for the push field bits. Each bit requires two time slots to encode the logic value of the bit. This encoding allows the detection of a single error at the time slot level. Bits are ...

  • Page 114

    ... Freescale Semiconductor, Inc. Motorola Interconnect Bus (MI BUS) 6.7.1 Controller detected errors There are three different MI BUS error types which are detected by the selected slave device and are not mutually exclusive. The MCU cannot determine which error occurred. 6.7.2 MCU detected errors There is a fourth error that can be detected by the MCU ...

  • Page 115

    ... Freescale Semiconductor, Inc. LOPS2 WOMS2 MIE2 M2 WAKE2 ILT2 PE2 PT2 TIE2 TCIE2 RIE2 ILIE2 TE2 RE2 RWU2 SBK2 Internal data bus MC68HC11P2 — Rev 1.0 For More Information On This Product, T8 Transmit buffer 10/11-bit TX shift register MIE2 Transmitter PT2 control TE2 SBK2 ...

  • Page 116

    ... Freescale Semiconductor, Inc. Motorola Interconnect Bus (MI BUS) 6.8 Interfacing to MI BUS Physically the MI BUS consists of only a single wire. In the example shown in components are required to connect up the MC68HC11P2 for full MI BUS operation. 4.7k¾ MCU 10k¾ Figure 6-4. A typical interface between the MC68HC11P2 and the MI BUS ...

  • Page 117

    ... Freescale Semiconductor, Inc. The MI BUS line can take two states, recessive or dominant. The recessive state (‘1’) is represented by 5V, through a pull-up resistor of 10k¾. The dominant state (‘0’) is represented by a maximum 0.3V (V CESAT The bus load depends on the number of devices on the bus. Each device has a pull-up resistor of 10k¾ ...

  • Page 118

    ... Freescale Semiconductor, Inc. Motorola Interconnect Bus (MI BUS) 6.10.1 INIT2 — EEPROM mapping and MI BUS delay register Address bit 7 EEPROM mapping (INIT2) $0037 This register sets the MI BUS delay time. INIT2 may be read at any time but bits 7–4 may be written only once after reset in normal modes (bits 3– ...

  • Page 119

    ... Freescale Semiconductor, Inc. 6.10.2 S2BDH, S2BDL — MI BUS clock rate control registers Address bit 7 SCI/MI 2/3 baud high (S2BDH) $0050 B2TST B2SPL SCI/MI 2/3 baud low (S2BDL) $0051 S2B7 S2B6 S2B5 S2B4 S2B3 S2B2 S2B1 S2B0 0000 0100 The contents of this register determine the clock rate for both MI BUS 2 and MI BUS 3. S2B[12:0] — ...

  • Page 120

    ... Freescale Semiconductor, Inc. Motorola Interconnect Bus (MI BUS) 6.10.4 S2CR2 — MI BUS2 control register 2 Address bit 7 SCI/MI 2 control 2 (S2CR2) $0053 RIE2 — Receiver interrupt enable BUS interrupt requested when RDRF2 flag is set RDRF2 and OR2 interrupts disabled. TE2 — Transmitter enable Transmitter enabled and port pin dedicated to the MI BUS. ...

  • Page 121

    ... Freescale Semiconductor, Inc. RDRF2 — Receive data register full flag Contents of the receiver serial shift register have been 0 = Contents of the receiver serial shift register have not been This bit is set when the contents of the receiver serial shift register have been transferred to the receiver data register. ...

  • Page 122

    ... Freescale Semiconductor, Inc. Motorola Interconnect Bus (MI BUS) 6.10.6 S2SR2 — MI BUS2 status register 2 Address bit 7 SCI/MI 2 status 2 (S2SR2) $0055 RAF — Receiver active flag (read only character is being received character is not being received. 6.10.7 S2DRL — MI BUS2 data register Address bit 7 ...

  • Page 123

    ... Freescale Semiconductor, Inc. 6.11 SCI/MI BUS3 registers The MI BUS2 and MI BUS3 modules share the MI BUS delay register (INIT2) at $0037 and the MI BUS2 clock rate register (S2BDH/L) at $0050–51. The two modules are functionally identical to one another and the registers for MI BUS3 are given here for reference purposes only ...

  • Page 124

    ... Freescale Semiconductor, Inc. Motorola Interconnect Bus (MI BUS) 6.11.5 S3DRL — MI BUS3 data register Address bit 7 SCI/MI 3 data low (S3DRL) $005F R7T7C R6T6C R5T5C R4T4C R3T3C R2T2C R1T1C R0T0C undefined Technical Data For More Information On This Product, bit 6 bit 5 bit Motorola Interconnect Bus (MI BUS) Go to: www ...

  • Page 125

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC11P2 Section 7. Serial Peripheral Interface (SPI) 7.1 Contents 7.2 7.3 7.4 7.5 7.6 7.7 7.2 Introduction The serial peripheral interface (SPI), an independent serial communications subsystem, allows the MCU to communicate synchronously with peripheral devices, such as transistor-transistor logic (TTL) shift registers, liquid crystal (LCD) display drivers, analog-to- digital converter subsystems, and other microprocessors ...

  • Page 126

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 7.3 Functional description The central element in the SPI system is the block containing the shift register and the read data buffer (see buffered in the transmit direction and double buffered in the receive direction. This means that new data for transmission cannot be written to the shifter until the previous transfer is complete ...

  • Page 127

    ... Freescale Semiconductor, Inc. optionally be used to indicate a multiple master bus contention. Refer to Figure MCU system clock Divider ÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128 SPI clock (master) Select OPT2 – Options register 2 SPI control SPSR – SPI status register SPI interrupt request MC68HC11P2 — ...

  • Page 128

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) SCK cycle # 1 (for reference) SCK (CPOL=0) SCK (CPOL=1) Sample input MSB Data out (CPHA=0) Sample input MSB Data out (CPHA=1) SS (to slave) Note: this figure shows the LSBF=0 (default) case. If LSBF=1, data is transferred in the reverse order (LSB first). ...

  • Page 129

    ... Freescale Semiconductor, Inc. 7.5 SPI signals The following paragraphs contain descriptions of the four SPI signals: master in slave out (MISO), master out slave in (MOSI), serial clock (SCK), and slave select (SS). Any SPI output line must have its corresponding data direction bit in DDRD register set. If the DDR bit is clear, that line is disconnected from the SPI logic and becomes a general-purpose input ...

  • Page 130

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) master device, select the clock rate slave device, SPR[1:0] have no effect on the operation of the SPI. 7.5.4 Slave select The slave select SS input of a slave device must be externally asserted before a master device can exchange data with the slave device. SS must be low before data transactions begin and must stay low for the duration of the transaction ...

  • Page 131

    ... Freescale Semiconductor, Inc. master, there is a chance of contention between two pin drivers. For push-pull CMOS drivers, this contention can cause permanent damage. The mode fault detection circuitry attempts to protect the device by disabling the drivers. The MSTR control bit in the SPCR and all four ...

  • Page 132

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 7.7 SPI registers The three SPI registers, SPCR, SPSR, and SPDR, provide control, status, and data storage functions. Refer to the following information for a description of how these registers are organized. 7.7.1 SPCR — Serial peripheral control register ...

  • Page 133

    ... Freescale Semiconductor, Inc. MSTR — Master mode select 1 = Master mode 0 = Slave mode CPOL — Clock polarity 1 = SCK is active low SCK is active high. When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master device has a steady state low value ...

  • Page 134

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 7.7.2 SPSR — Serial peripheral status register Address bit 7 SPI status (SPSR) $0029 SPIF — SPI interrupt complete flag 1 = Data transfer to external device has been completed valid completion of data transfer. SPIF is set upon completion of data transfer between the processor and the external device ...

  • Page 135

    ... Freescale Semiconductor, Inc. 7.7.3 SPDR — SPI data register Address bit 7 SPI data (SPDR) $002A (bit 7) The SPDR is used when transmitting or receiving data on the serial bus. Only a write to this register initiates transmission or reception of a byte, and this only occurs in the master device. At the completion of transferring a byte of data, the SPIF status bit is set in both the master and slave devices ...

  • Page 136

    ... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) IRVNE — Internal read visibility/not E (refer to On-Chip 1 = Data from internal reads is driven out of the external data bus visibility of internal reads on external bus. In single chip mode this bit determines whether the E clock drives out from the chip. ...

  • Page 137

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC11P2 8.1 Contents 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.2 Introduction The M68HC11 timing system is composed of five clock divider chains. The main clock divider chain includes a 16-bit free-running counter, which is driven by a programmable prescaler. The main timer’s programmable prescaler provides one of the four clocking rates to drive the 16-bit counter ...

  • Page 138

    ... Freescale Semiconductor, Inc. Timing System maximum count, the counter rolls over to $0000, sets an overflow flag and continues to increment. As long as the MCU is running in a normal operating mode, there is no way to reset, change or interrupt the counting. The capture/compare subsystem features three input capture channels, four output compare channels and one channel that can be selected to perform either input capture or output compare ...

  • Page 139

    ... Freescale Semiconductor, Inc. Control bits PR[1: 8.3 Timer structure The timer functions share I/O with all eight pins of port A: Figure 8-2 A pin control block includes logic for timer functions and for general- purpose I/O. For pins PA3, PA2, PA1 and PA0, this block contains both the edge-detection logic and the control logic that enables the selection of which edge triggers an input capture ...

  • Page 140

    ... Freescale Semiconductor, Inc. Timing System used for an output compare function, it cannot be written directly were a general-purpose output. Each of the output compare functions (OC[5:2]) is related to one of the port A output pins. Output compare 1 (OC1) has extra control logic, allowing it optional control of any combination of the PA[7:3] pins. The PA7 pin can be used as a general- purpose I/O pin input to the pulse accumulator OC1 output pin ...

  • Page 141

    ... Freescale Semiconductor, Inc. Prescaler ÷ MCU E clock PR[1:0] 16-bit timer bus EQ 16-bit comparator TOC1 (hi) TOC1 (lo) EQ 16-bit comparator TOC2 (hi) TOC2 (lo) EQ 16-bit comparator TOC3 (hi) TOC3 (lo) EQ 16-bit comparator TOC4 (hi) TOC4 (lo) EQ 16-bit comparator TI4/O5 (hi) TI4/O5 (lo) CLK 16-bit latch I4/O5 CLK 16-bit latch ...

  • Page 142

    ... Freescale Semiconductor, Inc. Timing System 8.4 Input capture The input capture function records the time an external event occurs by latching the value of the free-running counter when a selected edge is detected at the associated timer input pin. Software can store latched values and use them to compute the periodicity and duration of events. ...

  • Page 143

    ... Freescale Semiconductor, Inc. 8.4.1 TCTL2 — Timer control register 2 Address bit 7 Timer control 2 (TCTL2) $0021 EDG4BEDG4AEDG1BEDG1AEDG2BEDG2AEDG3BEDG3A 0000 0000 Use the control bits of this register to program input capture functions to detect a particular edge polarity on the corresponding timer input pin. Each of the input capture functions can be independently configured to detect rising edges only, falling edges only, any edge (rising or falling disable the input capture function ...

  • Page 144

    ... Freescale Semiconductor, Inc. Timing System 8.4.2 TIC1–TIC3 — Timer input capture registers Address bit 7 Timer input capture 1 (TIC1) high $0010 (bit 15) (14) Timer input capture 1 (TIC1) low $0011 (bit 7) Timer input capture 2 (TIC2) high $0012 (bit 15) (14) Timer input capture 2 (TIC2) low $0013 (bit 7) ...

  • Page 145

    ... Freescale Semiconductor, Inc. 8.4.3 TI4/O5 — Timer input capture 4/output compare 5 register Address bit 7 Capture 4/compare 5 (TI4/O5) $001E (bit 15) (14) high Capture 4/compare 5 (TI4/O5) $001F (bit 7) low Use TI4/O5 as either an input capture register or an output compare register, depending on the function chosen for the PA3 pin. To enable input capture pin, set the I4/O5 bit in the pulse accumulator control register (PACTL) to logic level one ...

  • Page 146

    ... Freescale Semiconductor, Inc. Timing System the free-running counter, independent of software latency. To generate an output signal of a specific frequency and duty cycle, repeat this pulse- generating procedure. There are four 16-bit read/write output compare registers: TOC1, TOC2, TOC3, and TOC4, and the TI4/O5 register, which functions under software control as either IC4 or OC5 ...

  • Page 147

    ... Freescale Semiconductor, Inc. 8.5.1 TOC1–TOC4 — Timer output compare registers Address bit 7 Timer output compare 1 (TOC1) $0016 (bit 15) (14) high Timer output compare 1 (TOC1) $0017 (bit 7) low Timer output compare 2 (TOC2) $0018 (bit 15) (14) high Timer output compare 2 (TOC2) $0019 (bit 7) ...

  • Page 148

    ... Freescale Semiconductor, Inc. Timing System 8.5.2 CFORC — Timer compare force register Address bit 7 Timer compare force (CFORC) $000B FOC1 FOC2 FOC3 FOC4 FOC5 The CFORC register allows forced early compares. FOC[1:5] correspond to the five output compares. These bits are set for each output compare that forced ...

  • Page 149

    ... Freescale Semiconductor, Inc. 8.5.4 OC1D — Output compare 1 data register Address bit 7 Output compare 1 data (OC1D) $000D OC1D7OC1D6OC1D5OC1D4OC1D3 Use this register with OC1 to specify the data that written to the affected pin of port A after a successful OC1 compare. When a successful OC1 compare occurs, a data bit in OC1D is written to the corresponding pin of port A for each bit that is set in OC1M. OC1D[7:3] — ...

  • Page 150

    ... Freescale Semiconductor, Inc. Timing System 8.5.6 TCTL1 — Timer control register 1 Address bit 7 Timer control 1 (TCTL1) $0020 The bits of this register specify the action taken as a result of a successful OCx compare. OM[2:5] — Output mode OL[2:5] — Output level These control bit pairs are encoded to specify the action taken after a successful OCx compare ...

  • Page 151

    ... Freescale Semiconductor, Inc. I4/O5I — Input capture 4/output compare 5 interrupt enable 1 = IC4/OC5 interrupt is enabled IC4/OC5 interrupt is disabled. When I4/O5 in PACTL is set, I4/O5I is the input capture 4 interrupt enable bit. When I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enable bit. IC1I–IC3I — Input capture x interrupt enable 1 = ICx interrupt is enabled ...

  • Page 152

    ... Freescale Semiconductor, Inc. Timing System IC1F–IC3F — Input capture x flag 1 = Selected edge has been detected on corresponding port pin Selected edge has not been detected on corresponding port These flags are set each time a selected active edge is detected on the ICx input line 8.5.9 TMSK2 — ...

  • Page 153

    ... Freescale Semiconductor, Inc. These bits are used to select the prescaler divide-by ratio. In normal modes, PR[1:0] can only be written once, and the write must be within 64 cycles after reset. See 8.5.10 TFLG2 — Timer interrupt flag register 2 Address bit 7 Timer interrupt flag 2 (TFLG2) ...

  • Page 154

    ... Freescale Semiconductor, Inc. Timing System 8.6 Real-time interrupt The real-time interrupt (RTI) feature, used to generate hardware interrupts at a fixed periodic rate, is controlled and configured by two bits (RTR1 and RTR0) in the pulse accumulator control (PACTL) register. The RTII bit in the TMSK2 register enables the interrupt capability. The four different rates available are a product of the MCU oscillator frequency and the value of bits RTR[1:0] ...

  • Page 155

    ... Freescale Semiconductor, Inc. 8.6.1 TMSK2 — Timer interrupt mask register 2 Address bit 7 Timer interrupt mask 2 (TMSK2) $0024 This register contains the real-time interrupt enable bit. NOTE: Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable the corresponding interrupt sources. ...

  • Page 156

    ... Freescale Semiconductor, Inc. Timing System 8.6.2 TFLG2 — Timer interrupt flag register 2 Address bit 7 Timer interrupt flag 2 (TFLG2) $0025 Bits of this register indicate the occurrence of timer system events. Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled or interrupt driven system ...

  • Page 157

    ... Freescale Semiconductor, Inc. 8.6.3 PACTL — Pulse accumulator control register Address bit 7 Pulse accumulator control $0026 (PACTL) Bits RTR[1:0] of this register select the rate for the RTI system. The remaining bits control the pulse accumulator and IC4/OC5 functions. Bits 7, 3 — Not implemented; always read zero PAEN — ...

  • Page 158

    ... Freescale Semiconductor, Inc. Timing System 8.8 Pulse accumulator The MC68HC11P2 has an 8-bit counter that can be configured to operate either as a simple event counter, or for gated time accumulation, depending on the state of the PAMOD bit in the PACTL register. Refer to the pulse accumulator block diagram, In the event counting mode, the 8-bit counter is clocked to increasing values by an external pin ...

  • Page 159

    ... Freescale Semiconductor, Inc. E/64 clock (from main timer) & PA7/ Input buffer OC1/ and edge detector PAI Output buffer From OC1 From DDRA7 Figure 8-3. Pulse accumulator block diagram Pulse accumulator control bits are also located within two timer registers, TMSK2 and TFLG2, as described in the following paragraphs. ...

  • Page 160

    ... Freescale Semiconductor, Inc. Timing System 8.8.1 PACTL — Pulse accumulator control register Address bit 7 Pulse accumulator control $0026 (PACTL) Four of this register’s bits control an 8-bit pulse accumulator system. Another bit enables either the OC5 function or the IC4 function, while two other bits select the rate for the real-time interrupt system. Bits [7, 3] — ...

  • Page 161

    ... Freescale Semiconductor, Inc. 8.8.2 PACNT — Pulse accumulator count register Address bit 7 Pulse accumulator count $0027 (bit 7) (PACNT) This 8-bit read/write register contains the count of external input events at the PAI input, or the accumulated count. In gated time accumulation mode, PACNT is readable even if PAI is not active. The counter is not affected by reset and can be read or written at any time ...

  • Page 162

    ... Freescale Semiconductor, Inc. Timing System are inhibited, and the system operates in a polled mode, which requires that PAOVF be polled by user software to determine when an overflow has occurred. When the PAOVI control bit is set, a hardware interrupt request is generated each time PAOVF is set. Before leaving the interrupt service routine, software must clear PAOVF by writing to the TFLG2 register. PAII and PAIF — ...

  • Page 163

    ... Freescale Semiconductor, Inc. for the PWM clock sources and enables the 16-bit PWM functions. The PWPOL register determines each channel’s polarity and selects the clock source for each channel. The PWSCAL register derives a user- scaled clock based on the A clock source, and the PWEN register enables the PWM channels ...

  • Page 164

    ... Freescale Semiconductor, Inc. Timing System CON34 PWEN3 PWEN4 CNT4 Clock CNT3 select PCLK3 PCLK4 PCLK1 PCLK2 CNT2 Clock CNT1 select CON12 PWEN1 PWEN2 reset reset carry reset reset carry Technical Data For More Information On This Product, PCKB1 PCKB2 PCKB3 Clock B ÷ ...

  • Page 165

    ... Freescale Semiconductor, Inc. 8.9.2 PWCLK — PWM clock prescaler and 16-bit select register Address bit 7 Pulse width clock select (PWCLK) $0060 CON34CON12PCKA2PCKA1 This register contains bits for selecting the 16-bit PWM options and for selecting the prescaler values for the clocks. ...

  • Page 166

    ... Freescale Semiconductor, Inc. Timing System CON12 — Concatenate Channels 1 and Channels 1 and 2 are concatenated into one 16-bit PWM 0 = Channels 1 and 2 are separate 8-bit PWMs. When concatenated, channel 1 is the high-order byte and the channel 2 pin (PH1) is the output. 8.9.2.2 Clock prescaler selection The three available clocks are clock A, clock B, and clock S (scaled) ...

  • Page 167

    ... Freescale Semiconductor, Inc. PCKA[2:1] 8.9.3 PWPOL — PWM timer polarity & clock source select register Address bit 7 Pulse width polarity select $0061 PCLK4 PCLK3 PCLK2 PCLK1 PPOL4 PPOL3 PPOL2 PPOL1 0000 0000 (PWPOL) PCLK[4:3] — Pulse width channel 4/3 clock select 1 = Clock S is source ...

  • Page 168

    ... Freescale Semiconductor, Inc. Timing System 8.9.4 PWSCAL — PWM timer prescaler register Address bit 7 Pulse width scale (PWSCAL) $0062 (bit 7) Scaled clock S is generated by dividing clock A by the value in PWSCAL, then dividing the result by two. If PWSCAL = $00, clock A is divided by 256, then divided by two to generate clock S. ...

  • Page 169

    ... Freescale Semiconductor, Inc. Bits [5:4] — Not implemented; always read zero PWEN[4:1] — Pulse width channels 4– Channel enabled on the associated port pin Channel disabled. 8.9.6 PWCNT1–4 — PWM timer counter registers Address bit 7 Pulse width count 1 (PWCNT1) $0064 (bit 7) ...

  • Page 170

    ... Freescale Semiconductor, Inc. Timing System 8.9.8 PWDTY1–4 — PWM timer duty cycle registers Address bit 7 Pulse width duty 1 (PWDTY1) $006C (bit 7) Pulse width duty 2 (PWDTY2) $006D (bit 7) Pulse width duty 3 (PWDTY3) $006E (bit 7) Pulse width duty 4 (PWDTY4) $006F (bit 7) There is one duty register for each channel. The value in this register determines the duty cycle of the associated PWM timer channel ...

  • Page 171

    ... Freescale Semiconductor, Inc. 8.9.9 Boundary cases The following boundary conditions apply to the values stored in the PWDTYx and PWPERx registers and the PPOLx bits: • • • • • • MC68HC11P2 — Rev 1.0 For More Information On This Product, If PWDTYx = $00, PWPERx > $00 and PPOLx = 0 then the output is always high. If PWDTYx = $00, PWPERx > ...

  • Page 172

    ... Freescale Semiconductor, Inc. Timing System Technical Data For More Information On This Product, Timing System Go to: www.freescale.com MC68HC11P2 — Rev 1.0 ...

  • Page 173

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC11P2 9.1 Contents 9.2 9.3 9.4 9.5 9.6 9.7 9.2 Introduction The analog-to-digital (A/D) system, a successive approximation converter, uses an all-capacitive charge redistribution technique to convert analog signals to digital values. The A/D converter shares input pins with port E: MC68HC11P2 — ...

  • Page 174

    ... Freescale Semiconductor, Inc. Analog-to-Digital Converter 9.3 Overview The A/D system is an 8-channel, 8-bit, multiplexed-input converter. The VDD AD and VSS AD pins are used to input supply voltage to the A/D converter. This allows the supply voltage to be bypassed independently. The converter does not require external sample and hold circuits because of the type of charge redistribution technique used ...

  • Page 175

    ... Freescale Semiconductor, Inc. 9.3.1 Multiplexer The multiplexer selects one of 16 inputs for conversion. Input selection is controlled by the value of bits CD – the ADCTL register. The eight port E pins are fixed-direction analog inputs to the multiplexer, and additional internal analog signal lines are routed to it. ...

  • Page 176

    ... Freescale Semiconductor, Inc. Analog-to-Digital Converter 9.3.2 Analog converter Conversion of an analog input selected by the multiplexer occurs in this block. It contains a digital-to-analog capacitor (DAC) array, a comparator, and a successive approximation register (SAR). Each conversion is a sequence of eight comparison operations, beginning with the most significant bit (MSB). Each comparison determines the value of a bit in the SAR ...

  • Page 177

    ... Freescale Semiconductor, Inc. 9.3.5 A/D converter clocks The CSEL bit in the OPTION register selects whether the A/D converter uses the system E clock or an internal RC oscillator for synchronization. When E clock frequency is below 750kHz, charge leakage in the capacitor array can cause errors, and the internal oscillator should be used ...

  • Page 178

    ... Freescale Semiconductor, Inc. Analog-to-Digital Converter An input voltage equal ratiometric conversions of this type, the source of each analog input should use V 9.4 A/D converter power-up and clock select ADPU (bit 7 of the OPTION register) controls A/D converter power up. Clearing ADPU removes power from and disables the A/D converter system ...

  • Page 179

    ... Freescale Semiconductor, Inc. After enabling the A/D power, at least 100µs should be allowed for system stabilization. CSEL — Clock select 1 = A/D and EEPROM use internal RC clock source (about 0 = A/D and EEPROM use system E clock (must be at least 1MHz). Selects alternate clock source for on-chip EEPROM and A/D charge pumps ...

  • Page 180

    ... Freescale Semiconductor, Inc. Analog-to-Digital Converter 9.5 Channel assignments The multiplexer allows the A/D converter to select one of sixteen analog signals. Eight of these channels correspond to port E input lines to the MCU, four others are internal reference points or test functions; the remaining four channels are reserved. Refer to 9 ...

  • Page 181

    ... Freescale Semiconductor, Inc. 9.5.2 Multiple-channel operation There are two types of multiple-channel operation. In the first type (SCAN = 0), a selected group of four channels is converted once only. The first result is stored in A/D result register 1 (ADR1), and the fourth result is stored in ADR4. After the fourth conversion is complete, all conversion activity is halted until a new conversion command is written to the ADCTL register ...

  • Page 182

    ... Freescale Semiconductor, Inc. Analog-to-Digital Converter SCAN — Continuous scan control 1 = A/D conversions take place continuously Each of the four conversions is performed only once. When this control bit is clear, the four requested conversions are performed once to fill the four result registers. When this control bit is set, conversions continue in a round-robin fashion with the result registers updated as data becomes available ...

  • Page 183

    ... Freescale Semiconductor, Inc. 9.6.2 ADR1–ADR4 — A/D converter results registers Address bit 7 A/D result 1 (ADR1) $0031 (bit 7) A/D result 2 (ADR2) $0032 (bit 7) A/D result 3 (ADR3) $0033 (bit 7) A/D result 4 (ADR4) $0034 (bit 7) These read-only registers hold an 8-bit conversion result. Writes to these registers have no effect ...

  • Page 184

    ... Freescale Semiconductor, Inc. Analog-to-Digital Converter 9.7 Operation in STOP and WAIT modes If a conversion sequence is in progress when either the STOP or WAIT mode is entered, the conversion of the current channel is suspended. When the MCU resumes normal operation, that channel is resampled and the conversion sequence is resumed. As the MCU exits the WAIT mode, the A/D circuits are stable and valid results can be obtained on the first conversion ...

  • Page 185

    ... Freescale Semiconductor, Inc. Technical Data — MC68HC11P2 10.1 Contents 10.2 10.3 10.4 10.5 10.6 10.7 10.2 Introduction Resets and interrupt operations load the program counter with a vector that points to a new location from which instructions are to be fetched. A reset immediately stops execution of the current instruction and forces the program counter to a known starting address ...

  • Page 186

    ... Freescale Semiconductor, Inc. Resets and Interrupts 10.3.1 Power-on reset A positive transition on VDD generates a power-on reset (POR), which is used only for power-up conditions. POR cannot be used to detect drops in power supply voltages. A 4064 t after the oscillator becomes active allows the clock generator to stabilize. If RESET is at logical zero at the end of 4064 t remains in the reset condition until RESET goes to logical one ...

  • Page 187

    ... Freescale Semiconductor, Inc. The state of the NOCOP bit in the CONFIG register determines whether the COP system is enabled or disabled. To change the enable status of the COP system, change the contents of the CONFIG register and then perform a system reset. In the special test and bootstrap operating modes, the COP system is initially inhibited by the disable resets (DISR) control bit in the TEST1 register ...

  • Page 188

    ... Freescale Semiconductor, Inc. Resets and Interrupts these two steps is possible as long as both steps are completed in the correct sequence before the timer times out. 10.3.5 Clock monitor reset The clock monitor circuit is based on an internal RC time delay MCU clock edges are detected within this RC time delay, the clock monitor can optionally generate a system reset ...

  • Page 189

    ... Freescale Semiconductor, Inc. 10.3.6 OPTION — System configuration options register 1 Address bit 7 System config. options 1 $0039 ADPU CSEL IRQE (OPTION) The special-purpose OPTION register sets internal system configuration options during initialization. The time protected control bits (IRQE, DLY, FCME and CR[1:0]) can be written to only once in the first 64 cycles after a reset and then they become read-only bits ...

  • Page 190

    ... Freescale Semiconductor, Inc. Resets and Interrupts This control bit can be read or written at any time and controls whether or not the internal clock monitor circuit triggers a reset sequence when the system clock is slow or absent. When it is clear, the clock monitor circuit is disabled, and when it is set, the clock monitor circuit is enabled ...

  • Page 191

    ... Freescale Semiconductor, Inc. These bits can be read at any time. The value read is the one latched into the register from the EEPROM cells during the last reset sequence. A new value programmed into this register is not readable until after a subsequent reset sequence. Unused bits always read as ones. ...

  • Page 192

    ... Freescale Semiconductor, Inc. Resets and Interrupts 10.4 Effects of reset When a reset condition is recognized, the internal registers and control bits are forced to an initial state. Depending on the cause of the reset and the operating mode, the reset vector can be fetched from any of six possible locations, as shown in Table 10-2 ...

  • Page 193

    ... Freescale Semiconductor, Inc. 10.4.3 Parallel I/O When a reset occurs in expanded operating modes, port B, C, and F pins used for parallel I/O are dedicated to the expansion bus reset occurs during a single chip operating mode, all ports are configured as general- purpose high-impedance inputs. NOTE: Do not confuse pin function with the electrical state of the pin at reset ...

  • Page 194

    ... Freescale Semiconductor, Inc. Resets and Interrupts 10.4.6 Pulse accumulator The pulse accumulator system is disabled at reset so that the pulse accumulator input (PAI) pin defaults to being a general-purpose input pin. 10.4.7 Computer operating properly (COP) The COP watchdog system is enabled if the NOCOP control bit in the CONFIG register is cleared, and disabled if NOCOP is set ...

  • Page 195

    ... Freescale Semiconductor, Inc. 10.4.10 Analog-to-digital converter The A/D converter configuration is indeterminate after reset. The ADPU bit is cleared by reset, which disables the A/D system. The conversion complete flag is cleared by reset. 10.4.11 System The EEPROM programming controls are disabled, so the memory system is configured for normal read operation. PSEL[4:0] are initialized with the binary value %00110, causing the external IRQ pin to have the highest I-bit interrupt priority ...

  • Page 196

    ... Freescale Semiconductor, Inc. Resets and Interrupts The maskable interrupt sources have the following priority arrangement: 1. IRQ 2. Real-time interrupt 3. Timer input capture 1 4. Timer input capture 2 5. Timer input capture 3 6. Timer output compare 1 7. Timer output compare 2 8. Timer output compare 3 9 ...

  • Page 197

    ... Freescale Semiconductor, Inc. 10.5.1 HPRIO — Highest priority I-bit interrupt and misc. register Address bit 7 Highest priority interrupt (HPRIO) $003C RBOOT, SMOD, and MDA bits depend on power-up initialization mode and can only be written in special modes when SMOD = 1. Refer to Table RBOOT — Read bootstrap ROM (refer to Chip 1 = Bootloader ROM enabled, at $BE40– ...

  • Page 198

    ... Freescale Semiconductor, Inc. Resets and Interrupts Technical Data For More Information On This Product, Table 10-3. Highest priority interrupt selection PSELx Interrupt source promoted reserved (default to IRQ reserved (default to IRQ reserved (default to IRQ IRQ (external pin Real-time interrupt Timer input capture Timer input capture 2 ...

  • Page 199

    ... Freescale Semiconductor, Inc. Vector address FFC0, C1 – FFD0, D1 reserved FFDA, DB FFDC, DD FFDE, DF FFEC, ED MC68HC11P2 — Rev 1.0 For More Information On This Product, Table 10-4. Interrupt and reset vector assignments Interrupt source • SCI/MI BUS3 receive data register full • SCI/MI BUS3 receiver overrun FFD2, D3 • ...

  • Page 200

    ... Freescale Semiconductor, Inc. Resets and Interrupts 10.6 Interrupts Excluding reset type interrupts, the MC68HC11P2 has 20 interrupt vectors that support 32 interrupt sources. The 17 maskable interrupts are generated by on-chip peripheral systems. These interrupts are recognized when the global interrupt mask bit (I) in the condition code register (CCR) is clear ...