MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 123

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.11 SCI/MI BUS3 registers
6.11.1 S3CR1 — MI BUS3 control register 1
6.11.2 S3CR2 — MI BUS3 control register 2
6.11.3 S3SR1 — MI BUS3 status register 1
6.11.4 S3SR2 — MI BUS3 status register 2
MC68HC11P2 — Rev 1.0
SCI/MI 3 control 2 (S3CR2)
SCI/MI 3 control 1 (S3CR1)
SCI/MI 3 status 1 (S3SR1)
SCI/MI 3 status 2 (S3SR2)
The MI BUS2 and MI BUS3 modules share the MI BUS delay register
(INIT2) at $0037 and the MI BUS2 clock rate register (S2BDH/L) at
$0050–51. The two modules are functionally identical to one another
and the registers for MI BUS3 are given here for reference purposes
only. All explanations of bit function can be found in the relevant section
of the MI BUS2 register descriptions.
Freescale Semiconductor, Inc.
Address bit 7
Address bit 7
Address bit 7
Address bit 7
For More Information On This Product,
$005B
$005C TDRE3 TC3 RDRF3 IDLE3 OR3
$005D
$005A LOPS3WOMS3 MIE3
Motorola Interconnect Bus (MI BUS)
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TIE3 TCIE3 RIE3
0
bit 6
bit 6
bit 6
bit 6
0
bit 5
bit 5
bit 5
bit 5
0
ILIE3
bit 4
bit 4
bit 4
bit 4
M3 WAKE3 ILT3
0
bit 3
bit 3
TE3
bit 3
bit 3
0
Motorola Interconnect Bus (MI BUS)
bit 2
RE3 RWU3 SBK3 0000 0000
bit 2
bit 2
NF3
bit 2
0
bit 1
PE3
bit 1
bit 1
bit 1
FE3
SCI/MI BUS3 registers
0
RAF3 0000 0000
bit 0
PT3 0000 0000
bit 0
bit 0
bit 0
PF3 1100 0000
Technical Data
on reset
on reset
on reset
on reset
State
State
State
State