MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 128
MC68HC711P2CFN4
Manufacturer Part Number
MC68HC711P2CFN4
Description
IC MCU 32K OTP 4MHZ 84-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet
1.MC711P2CFNE4.pdf
(268 pages)
Specifications of MC68HC711P2CFN4
Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Eeprom Size
640 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
84-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Manufacturer
Quantity
Price
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MOT
Quantity:
5 510
Company:
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MC68HC711P2CFN4
Manufacturer:
HITACHI
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10 000
Part Number:
MC68HC711P2CFN4
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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Serial Peripheral Interface (SPI)
7.4.1 Clock phase and polarity controls
Technical Data
Data out (CPHA=0)
Data out (CPHA=1)
SCK (CPOL=0)
SCK (CPOL=1)
(for reference)
Sample input
Sample input
SS (to slave)
SCK cycle #
Note: this figure shows the LSBF=0 (default) case. If LSBF=1, data is transferred in the reverse order (LSB first).
MSB
Software can select one of four combinations of serial clock phase and
polarity using two bits in the SPI control register (SPCR). The clock
polarity is specified by the CPOL control bit, which selects an active high
or active low clock, and has no significant effect on the transfer format.
The clock phase (CPHA) control bit selects one of two different transfer
formats. The clock phase and polarity should be identical for the master
SPI device and the communicating slave device. In some cases, the
phase and polarity are changed between transfers to allow a master
device to communicate with peripheral slaves having different
requirements.
When CPHA equals zero, the SS line must be deasserted and
reasserted between each successive serial byte. Also, if the slave writes
data to the SPI data register (SPDR) while SS is low, a write collision
error results.
When CPHA equals one, the SS line can remain low between
MSB
Freescale Semiconductor, Inc.
1
For More Information On This Product,
6
Figure 7-2. SPI transfer format
6
2
Serial Peripheral Interface (SPI)
Go to: www.freescale.com
5
5
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4
4
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1
LSB
MC68HC11P2 — Rev 1.0
8
LSB
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