MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 167

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.9.3 PWPOL — PWM timer polarity & clock source select register
MC68HC11P2 — Rev 1.0
Pulse width polarity select
(PWPOL)
PCLK[4:3] — Pulse width channel 4/3 clock select
PCLK[2:1] — Pulse width channel 2/1 clock select
PPOL[4:1] — Pulse width channel x polarity
Freescale Semiconductor, Inc.
Each channel has a polarity bit that allows a cycle to start with either
a high or a low level. This is shown on the block diagram,
as a selection of either the Q output or the Q output of the PWM output
flip flop. When one of the bits in the PWPOL register is set, the
associated PWM channel output is high at the beginning of the clock
cycle, then goes low when the duty count is reached.
PCKA[2:1]
Address bit 7
For More Information On This Product,
$0061 PCLK4 PCLK3 PCLK2 PCLK1 PPOL4 PPOL3 PPOL2 PPOL1 0000 0000
1 = Clock S is source.
0 = Clock B is source.
1 = Clock S is source.
0 = Clock A is source.
1 = PWM channel x output is high at the beginning of the clock
0 = PWM channel x output is low at the beginning of the clock cycle
0 0
0 1
1 0
1 1
cycle and goes low when duty count is reached.
and goes high when duty count is reached.
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Table 8-4. Clock A and clock B prescalers
Clock A
Timing System
E/2
E/4
E/8
bit 6
E
bit 5
bit 4
bit 3
Pulse-width modulation (PWM) timer
PCKB[3:1]
bit 2
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
bit 1
bit 0
Clock B
Technical Data
Timing System
E/128
E/16
E/32
E/64
Figure
E/2
E/4
E/8
E
on reset
State
8-4,