MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 168

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Timing System
8.9.4 PWSCAL — PWM timer prescaler register
8.9.5 PWEN — PWM timer enable register
Technical Data
Pulse width scale (PWSCAL)
Pulse width enable (PWEN)
Scaled clock S is generated by dividing clock A by the value in PWSCAL,
then dividing the result by two. If PWSCAL = $00, clock A is divided by
256, then divided by two to generate clock S.
Each timer has an enable bit to start its waveform output. Writing any of
these PWENx bits to one causes the associated port line to become an
output regardless of the state of the associated DDR bit. This does not
change the state of the DDR bit and when PWENx returns to zero the
DDR bit again controls I/O state. On the front end of the PWM timer the
clock is connected to the PWM circuit by the PWENx enable bit being
high. There is a synchronizing circuit to guarantee that the clock will only
be enabled or disabled at an edge.
PWEN contains 4 PWM enable bits — one for each channel. When an
enable bit is set to one, the pulse modulated signal becomes available
at the associated port pin.
TPWSL — PWM scaled clock test bit (Test mode only)
DISCP — Disable compare scaled E clock (Test mode only)
Freescale Semiconductor, Inc.
When TPWSL is one, clock S from the PWM timer is output to
PWSCAL register. Normal writing to the PWSCAL register still
functions.
Address bit 7
Address bit 7
For More Information On This Product,
$0062 (bit 7)
$0063 TPWSL DISCP
1 = Clock S output to PWSCAL register (Test only).
0 = Normal operation.
1 = Match of period does not reset associated count register (Test
Go to: www.freescale.com
Timing System
bit 6
bit 6
(6)
bit 5
bit 5
(5)
0
bit 4
bit 4
(4)
0
PWEN4PWEN3PWEN2PWEN10000 0000
bit 3
bit 3
(3)
bit 2
bit 2
(2)
MC68HC11P2 — Rev 1.0
bit 1
bit 1
(1)
(bit 0) 0000 0000
bit 0
bit 0
on reset
on reset
State
State