MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 176

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Analog-to-Digital Converter
9.3.2 Analog converter
9.3.3 Digital control
9.3.4 Result registers
Technical Data
Conversion of an analog input selected by the multiplexer occurs in this
block. It contains a digital-to-analog capacitor (DAC) array, a
comparator, and a successive approximation register (SAR). Each
conversion is a sequence of eight comparison operations, beginning
with the most significant bit (MSB). Each comparison determines the
value of a bit in the SAR.
The DAC array performs two functions. It acts as a sample and hold
circuit during the entire conversion sequence, and provides comparison
voltage to the comparator during each successive comparison.
The result of each successive comparison is stored in the SAR. When a
conversion sequence is complete, the contents of the SAR are
transferred to the appropriate result register.
A charge pump provides switching voltage to the gates of analog
switches in the multiplexer. Charge pump output must stabilize between
7 and 8 volts within up to 100 µs before the converter can be used. The
charge pump is enabled by the ADPU bit in the OPTION register.
All A/D converter operations are controlled by bits in register ADCTL. In
addition to selecting the analog input to be converted, ADCTL bits
indicate conversion status, and control whether single or continuous
conversions are performed. Finally, the ADCTL bits determine whether
conversions are performed on single or multiple channels.
Four 8-bit registers (ADR1 – ADR4) store conversion results. Each of
these registers can be accessed by the processor in the CPU. The
conversion complete flag (CCF) indicates when valid data is present in
the result registers. The result registers are written during a portion of the
system clock cycle when reads do not occur, so there is no conflict.
Freescale Semiconductor, Inc.
For More Information On This Product,
Analog-to-Digital Converter
Go to: www.freescale.com
MC68HC11P2 — Rev 1.0