MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 182

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Analog-to-Digital Converter
Technical Data
NOTE:
SCAN — Continuous scan control
MULT — Multiple-channel/single-channel control
When the multiple-channel continuous scan mode is used, extra care is
needed in the design of circuitry driving the A/D inputs. The charge on
the capacitive DAC array before the sample time is related to the voltage
on the previously converted channel. A charge share situation exists
between the internal DAC capacitance and the external circuit
capacitance. Although the amount of charge involved is small, the rate
at which it is repeated is every 64 µs for an E clock of 2 MHz. The RC
charging rate of the external circuit must be balanced against this charge
sharing effect to avoid errors in accuracy. Refer to the M68HC11
Reference Manual (M68HC11RM/AD) for further information.
CD–CA — Channel selects D–A
Freescale Semiconductor, Inc.
When this control bit is clear, the four requested conversions are
performed once to fill the four result registers. When this control bit is
set, conversions continue in a round-robin fashion with the result
registers updated as data becomes available.
When this bit is clear, the A/D converter system is configured to
perform four consecutive conversions on the single channel specified
by the four channel select bits CD–CA (bits 3–0 of the ADCTL
register). When this bit is set, the A/D system is configured to perform
a conversion on each of four channels where each result register
corresponds to one channel.
When a multiple channel mode is selected (MULT = 1), the two least
significant channel select bits (CB and CA) have no meaning and the
CD and CC bits specify which group of four channels is to be
converted.
For More Information On This Product,
1 = A/D conversions take place continuously.
0 = Each of the four conversions is performed only once.
1 = Each A/D channel has a result register allocated to it.
0 = Four consecutive conversions from the same A/D channel are
stored in the results registers.
Analog-to-Digital Converter
Go to: www.freescale.com
MC68HC11P2 — Rev 1.0