MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 183

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MC68HC711P2CFN4

Manufacturer Part Number
MC68HC711P2CFN4
Description
IC MCU 32K OTP 4MHZ 84-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC711P2CFN4

Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Eeprom Size
640 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
84-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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9.6.2 ADR1–ADR4 — A/D converter results registers
MC68HC11P2 — Rev 1.0
A/D result 1 (ADR1)
A/D result 2 (ADR2)
A/D result 3 (ADR3)
A/D result 4 (ADR4)
These read-only registers hold an 8-bit conversion result. Writes to these
registers have no effect. Data in the A/D converter result registers is valid
when the CCF flag in the ADCTL register is set, indicating a conversion
sequence is complete. If conversion results are needed sooner, refer to
Figure
Freescale Semiconductor, Inc.
Address bit 7
For More Information On This Product,
$0031 (bit 7)
$0032 (bit 7)
$0033 (bit 7)
$0034 (bit 7)
9-3, which shows the A/D conversion sequence diagram.
Analog-to-Digital Converter
Go to: www.freescale.com
Channel select
CD:CC:CB:CA
1. Used for factory testing.
control bits
bit 6
1 0 X X
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
(6)
(6)
(6)
(6)
bit 5
(5)
(5)
(5)
(5)
reserved
Channel
reserved
bit 4
V
(4)
(4)
(4)
(4)
signal
V
V
RH
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
RH
RL
/2
(1)
(1)
(1)
bit 3
(1)
(3)
(3)
(3)
(3)
Control, status and results registers
Result in ADRx
if MULT = 1
bit 2
(2)
(2)
(2)
(2)
ADR1
ADR2
ADR3
ADR4
ADR1
ADR2
ADR3
ADR4
ADR1
ADR2
ADR3
ADR4
Analog-to-Digital Converter
bit 1
(1)
(1)
(1)
(1)
(bit 0) undefined
(bit 0) undefined
(bit 0) undefined
(bit 0) undefined
bit 0
Technical Data
on reset
State

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