MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 188

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Resets and Interrupts
10.3.5 Clock monitor reset
Technical Data
these two steps is possible as long as both steps are completed in the
correct sequence before the timer times out.
The clock monitor circuit is based on an internal RC time delay. If no
MCU clock edges are detected within this RC time delay, the clock
monitor can optionally generate a system reset. The clock monitor
function is enabled or disabled by the CME control bit in the OPTION
register. The presence of a timeout is determined by the RC delay, which
allows the clock monitor to operate without any MCU clocks.
Clock monitor is used as a backup for the COP system. Because the
COP needs a clock to function, it is disabled when the clocks stop.
Therefore, the clock monitor system can detect clock failures not
detected by the COP system.
Semiconductor wafer processing causes variations of the RC timeout
values between individual devices. An E clock frequency below 10 kHz
is detected as a clock monitor error. An E clock frequency of 200 kHz or
more prevents clock monitor errors. Using the clock monitor function
when the E clock is below 200 kHz is not recommended.
Special considerations are needed when a STOP instruction is executed
and the clock monitor is enabled. Because the STOP function causes
the clocks to be halted, the clock monitor function generates a reset
sequence if it is enabled at the time the STOP mode was initiated. Before
executing a STOP instruction, clear the CME bit in the OPTION register
to zero to disable the clock monitor. After recovery from STOP, set the
CME bit to logic one to enable the clock monitor.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Resets and Interrupts
MC68HC11P2 — Rev 1.0