MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 190

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Resets and Interrupts
10.3.7 CONFIG — Configuration control register
Technical Data
Configuration control (CONFIG)
FCME — Force clock monitor enable
CR[1:0] — COP timer rate select bits
The internal E clock is first divided by 2
watchdog system. These control bits determine a scaling factor for the
watchdog timer. See
CONFIG controls the presence and location of EEPROM in the memory
map and enables the COP watchdog system. A security feature that
protects data in EEPROM and RAM is available on mask programmed
MCUs. Refer to
CONFIG is made up of EEPROM cells and static working latches. The
operation of the MCU is controlled directly by these latches and not the
EEPROM byte. When programming the CONFIG register, the EEPROM
byte is accessed. When the CONFIG register is read, the static latches
Freescale Semiconductor, Inc.
This control bit can be read or written at any time and controls whether
or not the internal clock monitor circuit triggers a reset sequence when
the system clock is slow or absent. When it is clear, the clock monitor
circuit is disabled, and when it is set, the clock monitor circuit is
enabled. Reset clears the CME bit.
In order to use both STOP and clock monitor, the CME bit should be
cleared before executing STOP, then set again after recovering from
STOP.
When FCME is set, slow or stopped clocks will cause a clock failure
reset sequence. To utilize STOP mode, FCME should always be
cleared.
Address bit 7
For More Information On This Product,
$003F ROMAD
1 = Clock monitor enabled; cannot be disabled until next reset.
0 = Clock monitor follows the state of the CME bit.
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Resets and Interrupts
RAM and EEPROM
bit 6
1
Table
bit 5
1
10-1.
PARENNOSECNOCOPROMON EEON x11x xxxx
bit 4
security.
bit 3
15
before it enters the COP
bit 2
MC68HC11P2 — Rev 1.0
bit 1
bit 0
on reset
State