MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 201

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10.6.2 Nonmaskable interrupt request (XIRQ)
MC68HC11P2 — Rev 1.0
can resume. Refer to
information.
Nonmaskable interrupts are useful because they can always interrupt
CPU operations. The most common use for such an interrupt is for
serious system problems, such as program runaway or power failure.
The XIRQ input is an updated version of the NMI (nonmaskable
interrupt) input of earlier MCUs.
Upon reset, both the X-bit and I-bit of the CCR are set to inhibit all
maskable interrupts and XIRQ. After minimum system initialization,
software can clear the X-bit by a TAP instruction, enabling XIRQ
interrupts. Thereafter, software cannot set the X-bit. Thus, an XIRQ
interrupt is a nonmaskable interrupt. Because the operation of the I-bit-
related interrupt structure has no effect on the X-bit, the internal XIRQ
pin remains unmasked. In the interrupt priority logic, the XIRQ interrupt
has a higher priority than any source that is maskable by the I-bit. All I-
bit-related interrupts operate normally with their own priority relationship.
When an I-bit-related interrupt occurs, the I-bit is automatically set by
hardware after stacking the CCR byte. The X-bit is not affected. When
an X-bit-related interrupt occurs, both the X and I bits are automatically
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 10-5. Stacking order on entry to interrupts
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Resets and Interrupts
Memory location
CPU Core and Instruction Set
SP – 1
SP – 2
SP – 3
SP – 4
SP – 5
SP – 6
SP – 7
SP – 8
SP
CPU registers
ACCA
ACCB
CCR
PCH
PCL
IYH
IXH
IYL
IXL
Resets and Interrupts
for further
Technical Data
Interrupts