MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 203

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10.6.6 Reset and interrupt processing
10.7 Low power operation
10.7.1 WAIT
MC68HC11P2 — Rev 1.0
The following flow diagrams illustrate the reset and interrupt process.
Figure 10-1
and how interrupt detection relates to normal opcode fetches.
3
and illustrate interrupt priorities.
interrupt sources within the SCI subsystem.
Both STOP and WAIT suspend CPU operation until a reset or interrupt
occurs. The WAIT condition suspends processing and reduces power
consumption to an intermediate level. The STOP condition turns off all
on-chip clocks and reduces power consumption to an absolute minimum
while retaining the contents of all bytes of the RAM.
The WAI opcode places the MCU in the WAIT condition, during which
the CPU registers are stacked and CPU processing is suspended until a
qualified interrupt is detected. The interrupt can be an external IRQ, an
XIRQ, or any of the internally generated interrupts, such as the timer or
serial interrupts. The on-chip crystal oscillator remains active throughout
the WAIT stand-by period.
The reduction of power in the WAIT condition depends on how many
internal clock signals driving on-chip peripheral functions can be shut
down. The CPU is always shut down during WAIT. While in the wait
state, the address/data bus repeatedly runs read cycles to the address
where the CCR contents were stacked. The MCU leaves the wait state
when it senses any interrupt that has not been masked.
The free-running timer system is shut down only if the I-bit is set to one
and the COP system is disabled by NOCOP being set to one. Several
other systems can also be in a reduced power consumption state
to
Freescale Semiconductor, Inc.
Figure 10-4
For More Information On This Product,
and
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Resets and Interrupts
Figure 10-2
provide an expanded version of a block in
illustrate how the CPU begins from a reset
Figure 10-6
shows the resolution of
Resets and Interrupts
Low power operation
Figure 10-1
Technical Data
Figure 10-