MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 229

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MC68HC11P2 — Rev 1.0
SUBD (opr)
SBCB (opr)
SUBA (opr)
SUBB (opr)
Mnemonic
STAA (opr)
STAB (opr)
STD (opr)
STS (opr)
STX (opr)
STY (opr)
STOP
SEC
SEV
SEI
Subtract with carry from B
Subtract memory from D
Subtract memory from A
Subtract memory from B
Store index register X
Store index register Y
Store accumulator A
Store accumulator B
Store accumulator D
Stop internal clocks
Store stack pointer
Set interrupt mask
Set overflow flag
Operation
Set carry
Table 11-2. Instruction set (Sheet 7 of 8)
Freescale Semiconductor, Inc.
For More Information On This Product,
A
D – M:M+1
B – M – C
SP
IX
IY
Description
A – M
B – M
CPU Core and Instruction Set
A
B
M; B
1
1
1
Go to: www.freescale.com
—
M:M+1
M:M+1
M:M+1
C
V
M
M
I
A
B
M+1
B
D
B IMM
B DIR
B EXT
B IND, X
B IND, Y
A DIR
A EXT
A IND, X
A IND, Y
B DIR
B EXT
B IND, X
B IND, Y
A IMM
A DIR
A EXT
A IND, X
A IND, Y
B IMM
B DIR
B EXT
B IND, X
B IND, Y
Addressing
INH
INH
INH
DIR
EXT
IND, X
IND, Y
INH
DIR
EXT
IND, X
IND, Y
DIR
EXT
IND, X
IND, Y
DIR
EXT
IND, X
IND, Y
IMM
DIR
mode
Opcode
18 E2
18 A7
18 E7
18 ED
18 AF
CDEF
18 DF
18 FF
1A EF
18 EF
18 A0
18 E0
C2
D2
F2
E2
0D
0F
0B
97
B7
A7
D7
F7
E7
DD
FD
ED
CF
9F
BF
AF
DF
FF
EF
80
90
B0
A0
C0
D0
F0
E0
83
93
Instruction
Operand
ii
dd
hh ll
ff
ff
—
—
—
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
hh ll
ff
ff
—
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
CPU Core and Instruction Set
Cycles
2
3
4
4
5
2
2
2
3
4
4
5
3
4
4
5
4
5
5
6
2
4
5
5
6
4
5
5
6
5
6
6
6
2
3
4
4
5
2
3
4
4
5
4
5
— — — —
— — — — — — — 1
— — — 1 — — — —
— — — — — — 1 —
— — — —
— — — —
— — — —
— — — — — — — —
— — — —
— — — —
— — — —
— — — —
— — — —
— — — —
S X H I N Z V C
Condition codes
Technical Data
Instruction set
0 —
0 —
0 —
0 —
0 —
0 —