MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 230

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MC68HC711P2CFN4

Manufacturer Part Number
MC68HC711P2CFN4
Description
IC MCU 32K OTP 4MHZ 84-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC711P2CFN4

Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Eeprom Size
640 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
84-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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CPU Core and Instruction Set
Operators
Cycles
Technical Data
Mnemonic
TST (opr)
XGDX
XGDY
TEST
TSTA
TSTB
TBA
TSX
TSY
TXS
TYS
SWI
TAB
TAP
TPA
WAI
+ Arithmetic addition, except where used as an
– Arithmetic subtraction, or negation symbol
† Infinite, or until reset occurs
‡ 12 cycles are used, beginning with the opcode
• Boolean AND
* Multiply
: Concatenation
Is transferred to
Exclusive-OR
inclusive-OR symbol in Boolean formulae
(Twos complement)
fetch. A wait state is entered, which remains
in effect for an integer number of MPU E clock
cycles (n) until an interrupt is recognized.
Finally, two additional cycles are used to fetch
the appropriate interrupt vector. (14 + n, total).
Transfer stack pointer to X
Transfer stack pointer to Y
Transfer X to stack pointer
Transfer Y to stack pointer
Transfer A to CC register
Transfer CC register to A
Test (only in test modes)
Test A for zero or minus
Test B for zero or minus
Test for zero or minus
Exchange D with X
Exchange D with Y
Software interrupt
Wait for interrupt
Transfer A to B
Transfer B to A
Operation
Table 11-2. Instruction set (Sheet 8 of 8)
Freescale Semiconductor, Inc.
For More Information On This Product,
address bus increments
stack registers & WAIT
IX
IY
see
SP + 1
SP + 1
IX – 1
IY – 1
Description
A
CCR
CPU Core and Instruction Set
Figure 11-2
A
B
Go to: www.freescale.com
M – 0
A – 0
B – 0
D; D
D; D
CCR
Condition Codes
B
A
SP
SP
A
IX
IY
Operands
IX
IY
dd
ff
hh
ii
jj
kk
ll
mm 8-bit mask (set bits to be affected)
rr
0
1
?
A INH
B INH
Addressing
8-bit direct address ($0000–$00FF); the high byte is assumed
to be zero
8-bit positive offset ($00 to $FF (0 to 256)) is added to the
contents of the index register
High order byte of 16-bit extended address
One byte of immediate data
High order byte of 16-bit immediate data
Low order byte of 16-bit immediate data
Low order byte of 16-bit extended address
Signed relative offset ($80 to $7F (–128 to +127));
offset is relative to the address following the offset byte
Bit not changed
Bit always cleared
Bit always set
Bit set or cleared, depending on the operation
Bit can be cleared, but cannot become set
Not defined
INH
INH
INH
INH
INH
INH
EXT
IND, X
IND, Y
INH
INH
INH
INH
INH
INH
INH
mode
Opcode
18 6D
18 30
18 35
18 8F
3F
16
06
17
00
07
7D
6D
4D
5D
30
35
3E
8F
Instruction
Operand
hh ll
ff
ff
Cycles
MC68HC11P2 — Rev 1.0
14
2
2
2
2
6
6
7
2
2
3
4
3
4
3
4
— — — 1 — — — —
— — — —
— — — —
— — — — — — — —
— — — — — — — —
— — — —
— — — —
— — — —
— — — — — — — —
— — — — — — — —
— — — — — — — —
— — — — — — — —
— — — — — — — —
— — — — — — — —
— — — — — — — —
S X H I N Z V C
Condition codes
0 —
0 —
0 0
0 0
0 0

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