MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 29

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MC68HC11P2 — Rev 1.0
NOTE:
BCS — Bus clock select
PLLON and BCS have built-in safeguards so that VCOOUT cannot be
selected as the clock source (BCS = 1) if the PLL is off (PLLON = 0).
Similarly, the PLL cannot be turned off (PLLON = 0) if it is on and in use
(BCS = 1). Turning the PLL on and selecting VCOOUT as the clock
source therefore requires two independent writes to PLLCR.
AUTO — Automatic bandwidth control
BWC — Bandwidth control
Freescale Semiconductor, Inc.
This bit activates the synthesizer circuit without connecting it to the
control circuit. This allows the circuit to stabilize before it drives the
CPU clocks. PLLON is set by reset, to allow the control loop to
stabilize during power up.
PLLON cannot be cleared whilst using VCOOUT to drive the internal
processor clock, i.e. when BCS is set.
This bit determines which signal drives the clock circuit generating the
bus clocks. Once BCS has been altered it can take up to [1.5 EXTAL
+ 1.5 VCOOUT] cycles for the change in the clock to occur. Reset
clears this bit.
AUTO selects between automatic bandwidth control circuits in the
phase detect block and manual bandwidth control. Reset sets this bit.
Bandwidth control is under manual control only when AUTO is clear.
(When AUTO is set, BWC acts as a read-only status bit to indicate
which mode has been selected by the internal circuit.) A delay of t
is required between changes to BWC. The low bandwidth driver is
always enabled, so this bit determines whether the high bandwidth
driver is on or off. On PLL start-up in automatic mode (AUTO = 1), the
high bandwidth driver is enabled (BWC = 1) by internal circuitry until
For More Information On This Product,
1 = VCOOUT output drives the clock circuit (4XCLK).
0 = EXTAL drives the clock circuit (4XCLK).
1 = Automatic bandwidth control selected.
0 = Manual bandwidth control selected.
1 = High bandwidth control selected.
0 = Low bandwidth control selected.
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Pin Descriptions
Phase-locked loop (XFC, VDDSYN)
Pin Descriptions
Technical Data
PLLS