MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 31

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.7.3.2 SYNR — Synthesizer program register
MC68HC11P2 — Rev 1.0
Synthesizer program (SYNR)
NOTE:
NOTE:
The PLL frequency synthesizer multiplies the frequency of the crystal
oscillator. The multiplication factor is software programmable via a loop
divider, which consists of a six-bit modulo N counter, with a further two
bit scaling factor.
The multiplication factor is given by 2(Y + 1)2
Y ð 63.
Exceeding recommended operating frequencies can result in
indeterminate MCU operation.
SYNX[1:0]
SYNY[5:0]
The resolution of the multiplication factors decreases by a factor of two,
as X increases:
Freescale Semiconductor, Inc.
Any interrupt, any reset, or the assertion of RAF in any of the SCIs will
allow the PLL to resume operating at the frequency specified in the
SYNR. The user must set BCS after the PLL has had time to adjust
(t
become set, hence the PLL will not resume normal operation.
These bits program the binary taps (divide by 1, 2, 4 and 8). Reset
clears these bits.
These bits program the six-bit modulo N (1 to 64) counter. Reset sets
these bits to %001011.
PLLS
Address bit 7
For More Information On This Product,
$002F SYNX1SYNX0 SYNY5SYNY4SYNY3SYNY2 SYNY1 SYNY0 0000 1011
). If, for a specific SCI, the RE bit is clear, then RAF cannot
Go to: www.freescale.com
Pin Descriptions
X
0
1
2
3
bit 6
bit 5
0 – 63
0 – 63
0 – 63
0 – 63
Y
bit 4
16, 32, 48, 64, …, 1024
Possible multipliers
8, 16, 24, 32, …, 512
4, 8, 12, 16, …, 256
2, 4, 6, 8, …, 128
bit 3
Phase-locked loop (XFC, VDDSYN)
bit 2
X
, where 0 ð X ð 3 and 0 ð
bit 1
bit 0
Pin Descriptions
Technical Data
on reset
State