MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 65

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.6.1.2 EPROM programming
MC68HC11P2 — Rev 1.0
NOTE:
EXCOL — Select extra columns
EXROW — Select extra rows
EPGM — EPROM program command
If ELAT = 0 (normal operation) then EPGM = 0 (programming voltage
disconnected).
The EPROM may be programmed and verified in software, via the MCU,
using the following procedure. The ROMON bit in the CONFIG register
should be set. On entry, A contains the data to be programmed and X
contains the EPROM address.
EPROG
With this method, the EPROM is programmed by software while in the
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The extra column may be accessed at bit 7; addresses use bits 11–5,
bits 4–0 must be ones. The EXCOL bit always reads zero in normal
modes and may be read or written only in special modes.
There are four extra rows (two in each block). Addresses use bits 6–0,
bits 11–7 must be zeros. (The high nibble determines which 16k block
is accessed.) The EXROW bit always reads zero in normal modes
and may be read or written only in special modes.
This bit can be read at any time, but may only be written if ELAT is set.
For More Information On This Product,
1 = User array disabled; extra column selected.
0 = User array selected.
1 = User array disabled; extra rows selected.
0 = User array selected.
1 = Programming voltage (V
0 = Programming voltage (V
Operating Modes and On-Chip Memory
LDAB
STAB
STAA
LDAB
STAB
JSR
CLR
array.
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#$20
$102B
$0, X
#$21
$102B
DLYEP
$102B
Set ELAT bit (PGM=0) to enable EPROM latches.
Store data to EPROM address
Set EPGM bit, with ELAT=1, to enable prog. voltage
Delay 2–4 ms
Turn off programming voltage and set to READ mode
PPE
PPE
EPROM, EEPROM and CONFIG register
) switched to the EPROM array.
) disconnected from the EPROM
Operating Modes and On-Chip Memory
Technical Data