MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 91

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.6 Wakeup feature
5.6.1 Idle-line wakeup
MC68HC11P2 — Rev 1.0
The wakeup feature reduces SCI service overhead in multiple receiver
systems. Software for each receiver evaluates the first character or
frame of each message. All receivers are placed in wakeup mode by
writing a one to the RWU bit in the SCCR2 register. When RWU is set,
the receiver-related status flags (RDRF, IDLE, OR, NF, FE, and PF) are
inhibited (cannot be set). Although RWU can be cleared by a software
write to SCCR2, to do so would be unusual. Normally RWU is set by
software and is cleared automatically with hardware. Whenever a new
message begins, logic alerts the dormant receivers to wake up and
evaluate the initial character of the new message.
Two methods of wakeup are available: idle-line wakeup and address
mark wakeup. During idle-line wakeup, a dormant receiver activates as
soon as the RXD line becomes idle. In the address mark wakeup, logic
one in the most significant bit (MSB) of a character activates all sleeping
receivers. To use either receiver wakeup method, establish a software
addressing scheme to allow the transmitting devices to direct messages
to individual receivers or to groups of receivers. This addressing scheme
can take any form as long as all transmitting and receiving devices are
programmed to understand the same scheme.
Clearing the WAKE bit in SCCR1 register enables idle-line wakeup
mode. In idle-line wakeup mode, all receivers are active (RWU bit in
SCCR2 = 0) when each message begins. The first frames of each
message are addressing frames. Each receiver in the system evaluates
the addressing frames of a message to determine if the message is
intended for that receiver. When a receiver finds that the message is not
intended for it, it sets the RWU bit. Once set, the RWU control bit
disables all but the necessary receivers for the remainder of the
message, thus reducing software overhead for the remainder of that
message. As soon as an idle line is detected by receiver logic, hardware
automatically clears the RWU bit so that the first frames of the next
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Serial Communications Interface (SCI)
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Serial Communications Interface (SCI)
Wakeup feature
Technical Data