MC68HC908GP32CB Freescale Semiconductor, MC68HC908GP32CB Datasheet
MC68HC908GP32CB
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MC68HC908GP32CB Summary of contents
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MC68HC908GP32 Data Sheet M68HC08 Microcontrollers MC68HC908GP32 Rev. 10 1/2008 freescale.com ...
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...
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... The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. ...
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... Added unused pins note — Replaced SCI block diagram — Replaced SCI MC68HC908GP32 Data Sheet, Rev. 10 Page Number(s) 199 337 387 397 341 393 Throughout 46 250 123 N/A N/A N/A N 103 105 115 — Removed 131 133 135 Freescale Semiconductor ...
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... Table 17-3. Mode, Edge, and Level Selection compare to mode table Chapter 18 Development Support monitor mode chapters into Development Support Chapter Freescale Semiconductor Description — Replaced SCI receiver — Corrected Break — Updated SIM reset status register — Replaced SPI module block — ...
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... Revision History 6 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
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... Chapter 14 System Integration Module (SIM .157 Chapter 15 Serial Peripheral Interface Module (SPI .175 Chapter 16 Timebase Module (TBM .195 Chapter 17 Timer Interface Module (TIM .199 Chapter 18 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 Chapter 19 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 Chapter 20 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255 Chapter 21 Ordering Information .263 Freescale Semiconductor MC68HC908GP32 Data Sheet, Rev ...
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... List of Chapters 8 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
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... FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.6.4 FLASH Mass Erase Operation 2.6.5 FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.6.6 FLASH Block Protection 2.6.6.1 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.6.7 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Freescale Semiconductor Chapter 1 General Description and and DDA SSA /V and V DDAD REFH ...
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... Timer Interface Module (TIM1 and TIM2 3.12.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.12.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.13 Timebase Module (TBM 3.13.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.13.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.14 Exiting Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.15 Exiting Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10 Chapter 3 Low-Power Modes MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
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... Oscillator Enable Signal (SIMOSCEN 5.4.7 Oscillator Stop Mode Enable Bit (OSCSTOPENB 5.4.8 Crystal Output Frequency Signal (CGMXCLK 5.4.9 CGM Base Clock Output (CGMOUT Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ADC) )/ADC Voltage Reference High Pin (V DDAD )/ADC Voltage Reference Low Pin (V SSAD ) ...
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... COPRS (COP Rate Select 7.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12 Chapter 6 Configuration Register (CONFIG) Chapter 7 Computer Operating Properly (COP) MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
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... Keyboard Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 10.4.1 MODEK = 106 10.4.2 MODEK = 106 10.4.3 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 10.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 10.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Freescale Semiconductor Chapter 8 Central Processor Unit (CPU) Chapter 9 External Interrupt (IRQ) Chapter 10 Keyboard Interrupt (KBI) Module MC68HC908GP32 Data Sheet, Rev ...
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... Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.5.2 Data Direction Register 125 12.5.3 Port D Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 12.6 Port 127 12.6.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 12.6.2 Data Direction Register 128 14 Chapter 11 Low-Voltage Inhibit (LVI) Chapter 12 Input/Output (I/O) Ports MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
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... SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.2.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.2.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Freescale Semiconductor Chapter 13 Chapter 14 System Integration Module (SIM) MC68HC908GP32 Data Sheet, Rev ...
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... Transmission Format When CPHA = 180 15.5.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 15.6 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.7.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.7.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 15.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.9 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 16 Chapter 15 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
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... Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 17.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 17.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 17.7 TIM During Break Interrupts 207 Freescale Semiconductor Chapter 16 Timebase Module (TBM) Chapter 17 Timer Interface Module (TIM) MC68HC908GP32 Data Sheet, Rev ...
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... DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 19.7 5.0-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 19.8 3.0-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 19.9 Output High-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 19.10 Output Low-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 19.11 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 18 Chapter 18 Development Support Chapter 19 Electrical Specifications MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
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... Clock Generation Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 19.16.1 CGM Component Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 19.16.2 CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 19.17 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 21.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Freescale Semiconductor Chapter 20 Mechanical Specifications Chapter 21 Ordering Information MC68HC908GP32 Data Sheet, Rev ...
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... Table of Contents 20 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
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... Serial peripheral interface module (SPI) • Serial communications interface module (SCI security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor (1) MC68HC908GP32 Data Sheet, Rev ...
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... Memory-to-memory data transfers Fast 8 × 8 multiply instruction • • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 22 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
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... POWER V DDA V SSA † Ports are software configurable with pullup device if input port. ‡ Higher current drive port pins * Pin contains integrated pullup device Freescale Semiconductor INTERNAL BUS PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE 8-BIT KEYBOARD ...
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... PTC6 Connected to ground PTD6/T2CH0 PTD7/T2CH1 MC68HC908GP32 Data Sheet, Rev. 10 PTA7/KBD7 PTA6/KBD6 PTA5/KBD5 PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 V /V (ADC) SSAD REFL V /V (ADC) DDAD REFH PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTD5/T1CH1 PTD4/T1CH0 Internal Connection Unconnected Unconnected Freescale Semiconductor ...
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... V (PLL) DDA V (PLL) SSA CGMXFC (PLL) OSC2 OSC1 PTC0 PTC1 PTC2 PTC3 PTC4 PTE0/TxD PTE1/RxD PTD0/SS PTD1/MISO PTD2/MOSI PTD3/SPSCK PTD4/T1CH0 Figure 1-3. 42-Pin SDIP Pin Assignments Freescale Semiconductor RST IRQ Pins Not Available on 42-Pin Package PTC5 Connected to ground PTC6 Connected to ground MC68HC908GP32 Data Sheet, Rev ...
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... C1 optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. 26 and MC68HC908GP32 Data Sheet, Rev. 10 PTA1/KBD1 33 PTA0/KBD0 SSAD REFL DDAD REFH PTB7/AD7 29 PTB6/AD6 28 PTB5/AD5 27 PTB4/AD4 26 PTB3/AD3 25 PTB2/AD2 24 PTB1/AD1 23 Figure 1-5 Freescale Semiconductor ...
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... CGMXFC is an external filter capacitor connection for the CGM. See (CGM) 1.5.7 ADC Power Supply/Reference Pins (V V and V are the power supply pins for the analog-to-digital converter (ADC). Connect the V DDAD SSAD pin to the same voltage potential as V Freescale Semiconductor MCU 0.1 µ ...
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... Chapter 17 Timer Interface Module Chapter 12 Input/Output (I/O) Chapter 13 Serial Communications Interface Module Ports. MC68HC908GP32 Data Sheet, Rev the low DDAD REFL . and Chapter Chapter 4 Analog-to-Digital Chapter 12 Input/Output (I/O) Ports. (TIM), Chapter 15 Serial Ports. PTD6 and PTD7 are only Freescale Semiconductor ...
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... BRKSCR • $FE0C; LVI status register, LVISR • $FF7E; FLASH block protect register, FLBPR • $FFFF; COP control register, COPCTL Data registers are shown in Figure Freescale Semiconductor 2-2. Table 2 list of vector locations. MC68HC908GP32 Data Sheet, Rev. 10 Figure 2-1, includes: (Figure 2-1) ...
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... A-Family Parts $FE20 Monitor ROM ↓ 307 Bytes $FF52 $FF53 Unimplemented ↓ 43 Bytes $FF7D $FF7E FLASH Block Protect Register (FLBPR) $FF7F Unimplemented ↓ 93 Bytes $FFDB $FFDC FLASH Vectors ↓ 36 Bytes $FFFF Figure 2-1. Memory Map MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
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... Read: Data Direction Register E $000C Write: (DDRE) Reset: Read: Port A Input Pullup Enable $000D Register Write: (PTAPUE) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit PTA7 PTA6 PTA5 PTA4 Unaffected by reset PTB7 PTB6 PTB5 PTB4 Unaffected by reset ...
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... MC68HC908GP32 Data Sheet, Rev Bit CPHA SPWOM SPE SPTIE SPTE MODFEN SPR1 SPR0 WAKE ILTY PEN PTY RWU SBK ORIE NEIE FEIE PEIE BKF RPF SCR2 SCR1 SCR0 KEYF 0 IMASKK MODEK ACKK KBIE3 KBIE2 KBIE1 KBIE0 TBIE TBON R TACK Unaffected Freescale Semiconductor ...
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... Read: Timer 1 Channel 1 Status and $0028 Write: Control Register (T1SC1) Reset: Read: Timer 1 Channel 1 $0029 Register High Write: (T1CH1H) Reset: Read: Timer 1 Channel 1 $002A Register Low Write: (T1CH1L) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit COPRS ...
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... R = Reserved MC68HC908GP32 Data Sheet, Rev Bit 0 0 PS2 PS1 PS0 Bit Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit Bit 0 ELS1B ELS1A TOV1 CH1MAX Bit Bit 0 PRE1 PRE0 VPR1 VPR0 MUL11 MUL10 MUL9 MUL8 MUL3 MUL2 MUL1 MUL0 Unaffected Freescale Semiconductor ...
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... Write: (INT1) Reset: Read: Interrupt Status Register 2 $FE05 Write: (INT2) Reset: Read: Interrupt Status Register 3 $FE06 Write: (INT3) Reset: Read: $FE07 Reserved Write: Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit VRS7 VRS6 VRS5 VRS4 COCO ...
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... Bit BRKE BRKA LVIOUT BPR7 BPR6 BPR5 BPR4 Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented R = Reserved MC68HC908GP32 Data Sheet, Rev Bit 0 HVEN MASS ERASE PGM Bit Bit BPR3 BPR2 BPR1 BPR0 Unaffected Freescale Semiconductor ...
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... Vector Priority Lowest Highest Freescale Semiconductor . Table 2-1. Vector Addresses Vector Address $FFDC Timebase Vector (High) IF16 $FFDD Timebase Vector (Low) $FFDE ADC Conversion Complete Vector (High) IF15 $FFDF ADC Conversion Complete Vector (Low) $FFE0 Keyboard Vector (High) IF14 $FFE1 Keyboard Vector (Low) ...
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... FLASH control register. ; • $FFDC–$FFFF; these locations are reserved for user-defined interrupt and reset vectors. Programming tools are available from Freescale. Contact your local Freescale representative for more information. 38 NOTE NOTE NOTE MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
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... Write any data to any FLASH location within the page address range of the block to be erased. (min. 10 µs) 4. Wait for a time, t nvs 5. Set the HVEN bit security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor NOTE ...
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... When in Monitor mode, with security sequence failed of any FLASH address. 40 NOTE (1) within the FLASH memory address range. NOTE NOTE (see 18.3.2 Security), write to the FLASH block protect register instead MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
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... HV t NVS Refer to 19.17 Memory The time between programming the FLASH address change (step 7 to step 7), or the time between the last FLASH programmed to clearing the Freescale Semiconductor NOTE NOTE NOTE NOTE NOTE maximum or t maximum. t PROG HV x 64) ≤ ...
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... When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations. In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit 42 NOTE NOTE MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
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... PROG This row program algorithm assumes the row programmed are initially erased. Figure 2-4. FLASH Programming Flowchart Freescale Semiconductor 1 Set PGM bit 2 Read the FLASH block protect register 3 Write any data to any FLASH address ...
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... With this mechanism, the protect start address can be XX00 and XX80 (128 bytes page boundaries) within the FLASH memory. Start address of FLASH block protect Figure 2-6. FLASH Block Protect Start Address 44 NOTE BPR6 BPR5 BPR4 BPR3 16-bit memory address 1 FLBPR value MC68HC908GP32 Data Sheet, Rev the TST 2 1 Bit 0 BPR2 BPR1 BPR0 Freescale Semiconductor ...
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... Standby Mode is the power saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH minimum. Freescale Semiconductor Start of Address of Protect Range The entire FLASH memory is protected. $8080 (1000 0000 1000 0000) $8100 (1000 0001 0000 0000) and so on ...
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... Memory 46 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
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... Wait Mode If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if the SBSW bit in the break status register is set. Freescale Semiconductor MC68HC908GP32 Data Sheet, Rev. 10 Chapter 6 Configuration Register ...
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... Computer Operating Properly Module (COP) 3.6.1 Wait Mode The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. 48 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
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... MCU out of wait mode. 3.9.2 Stop Mode If enabled, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. Freescale Semiconductor MC68HC908GP32 Data Sheet, Rev. 10 External Interrupt Module (IRQ) 49 ...
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... WAIT instruction. 3.12.2 Stop Mode The TIM is inactive in stop mode. The STOP instruction does not affect register states or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt. 50 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
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... Timer 2 interface module (TIM2) interrupt — A CPU interrupt request from the TIM2 loads the program counter with the contents of: – $FFEC and $FFED; TIM2 overflow – $FFEE and $FFEF; TIM2 channel 1 – $FFF0 and $FFF1; TIM2 channel 0 Freescale Semiconductor MC68HC908GP32 Data Sheet, Rev. 10 Timebase Module (TBM) voltage resets the tripf 51 ...
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... Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32 CGMXCLK cycles. Use the full stop recovery time (SSREC = 0) in applications that use an external crystal. 52 NOTE MC68HC908GP32 Data Sheet, Rev. 10 voltage resets the MCU tripf Freescale Semiconductor ...
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... Inside the ADC module, the reference voltages V ADC analog power, V ground Therefore, the ADC input voltage should not exceed these SSAD analog supply voltages. Freescale Semiconductor 4-1.) , the ADC converts the signal to $FF (full scale). If the REFH NOTE REFH ; and V ...
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... ADIV2–ADIV0 ADICLK Figure 4-1. ADC Block Diagram NOTE pin to the same voltage potential as the V pin to the same voltage potential as the ADC cycles ADC frequency MC68HC908GP32 Data Sheet, Rev. 10 DISABLE PTBx ADC CHANNEL x ADCH4–ADCH0 CHANNEL SELECT pin, and DD pin. SS Freescale Semiconductor ...
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... The ADC analog portion uses V potential External filtering may be necessary to ensure clean V DD For maximum noise immunity, route V capacitors as close as possible to the package. Freescale Semiconductor )/ADC Voltage Reference High Pin (V DDAD as its power pin. Connect the V DDAD NOTE carefully and place bypass DDAD MC68HC908GP32 Data Sheet, Rev ...
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... Voltage Reference Low Pin (V SSAD as its ground pin. Connect the V SSAD NOTE cleanly to avoid any offset errors. SSAD ) AIEN ADCO ADCH4 ADCH3 NOTE MC68HC908GP32 Data Sheet, Rev REFL pin to the same voltage SSAD 2 1 Bit 0 ADCH2 ADCH1 ADCH0 Freescale Semiconductor ...
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... ADC converter both in production test and for user applications. ADCH4 ADCH3 ↓ ↓ NOTE: If any unused channels are selected, the resulting ADC conversion will be unknown or reserved. Freescale Semiconductor Table 4-1.) NOTE Table 4-1. Mux Channel Select ADCH2 ADCH1 ADCH0 ...
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... Table 4-2. ADC Clock Divide Ratio ADIV1 ADIV0 ADC Clock Rate ADC input clock ÷ ADC input clock ÷ ADC input clock ÷ ADC input clock ÷ ADC input clock ÷ MC68HC908GP32 Data Sheet, Rev Bit 0 AD2 AD1 AD0 Bit Freescale Semiconductor ...
Page 59
... ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be guaranteed Internal bus clock 0 = External clock (CGMXCLK) ADC input clock frequency ----------------------------------------------------------------------- - ADIV 2 ADIV 0 Freescale Semiconductor = 1MHz – MC68HC908GP32 Data Sheet, Rev. 10 I/O Registers 59 ...
Page 60
... Analog-to-Digital Converter (ADC) 60 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 61
... Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK. Figure 5-1 shows the structure of the CGM. Freescale Semiconductor MC68HC908GP32 Data Sheet, Rev ...
Page 62
... CONTROL CONTROL AUTO ACQ PLLIE PLLF PRE1–PRE0 P 2 FREQUENCY DIVIDER Figure 5-1. CGM Block Diagram MC68HC908GP32 Data Sheet, Rev. 10 CGMXCLK (TO: SIM, TIMTB15A, ADC) A CGMOUT CLOCK ÷ (TO SIM) SELECT CIRCUIT SIMDIV2 *WHEN (FROM SIM) CGMOUT = B E CGMVCLK PLLIREQ (TO SIM) Freescale Semiconductor ...
Page 63
... P and the modulo divider reduces the VCO clock by a factor, N. The dividers’ output is the VCO feedback clock, CGMVDV, running at a frequency, f Programming the PLL for more information.) Freescale Semiconductor VRS , (38.4 kHz) times a linear factor, L, and a power-of-two factor VCLK MC68HC908GP32 Data Sheet, Rev ...
Page 64
... Modes. The value of the external capacitor and the 5.5.2 PLL Bandwidth Control 5.3.8 Base Clock Selector Circuit.) The PLL is automatically in Register read-only indicator of the mode of Modes.) 5.8 Acquisition/Lock Time Specifications MC68HC908GP32 Data Sheet, Rev. 10 Register.) 5.5.2 PLL 5.3.8 Base Clock Selector Circuit.) 5.6 for Freescale Semiconductor ...
Page 65
... See Specifications. Choose the reference divider After choosing N and P, the actual bus frequency can be determined using equation in 2 above. Freescale Semiconductor 5.8 Acquisition/Lock Time Specifications Register.) , after entering tracking mode before selecting the PLL as the ...
Page 66
... VCLK ⎜ ⎟ round -------------------------- E ⎝ ⎠ × NOM MC68HC908GP32 Data Sheet, Rev integer divisor of f RCLK ⎛ ⎞ f ⎫ VCLKDES ⎜ ⎟ ⎬ ------------------------- - f ⎝ ⎠ ⎭ RCLK ⎞ ⎟ ⎠ ⎞ ⎟ ⎠ and f . VCLK BUS Freescale Semiconductor , BUSDES ...
Page 67
... The values for and R can only be programmed when the PLL is off (PLLON = 0). Table 5-1 provides numeric examples (numbers are in hexadecimal notation): f BUS 2.0 MHz 2.4576 MHz 2.5 MHz 4.0 MHz 4.9152 MHz 5.0 MHz 7.3728 MHz 8.0 MHz Freescale Semiconductor E ( × VRS NOM E × ...
Page 68
... Routing should be done with great care to minimize signal cross talk and noise. See 19.16.1 CGM Component Specifications 68 5.3.6 Programming the PLL Circuit.) for capacitor and resistor values. MC68HC908GP32 Data Sheet, Rev. 10 does not account for three possible Figure Freescale Semiconductor 5-2. ...
Page 69
... The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is connected to this pin. (See Figure To prevent noise problems, the filter network should be placed as close to the CGMXFC pin as possible, with minimum routing distances and no routing of other signals across the network. Freescale Semiconductor CGMXCLK OSC2 CGMXFC 10 kΩ RS 0.033 µ ...
Page 70
... CGMINT is the interrupt signal generated by the PLL lock detector DDA NOTE ) SSA NOTE Figure 5-2 shows only the logical relation of CGMXCLK to OSC1 MC68HC908GP32 Data Sheet, Rev. 10 pin to the same voltage DDA pin to the same voltage SSA ) and comes XCLK Freescale Semiconductor ...
Page 71
... When AUTO = 0, PLLF and LOCK read as clear. 3. When AUTO = 1, ACQ is read-only. 4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only. 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only. Freescale Semiconductor Register.) High.) Low.) Register.) Register.) ...
Page 72
... PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock PLLF PLLON BCS PRE1 NOTE NOTE MC68HC908GP32 Data Sheet, Rev Bit 0 PRE0 VPR1 VPR0 5.3.8 Base Clock 5.3.8 Base Clock Freescale Semiconductor ...
Page 73
... Indicates when the PLL is locked • In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode • In manual operation, forces the PLL into acquisition or tracking mode Freescale Semiconductor Circuit.) PLL.) PRE1 and PRE0 cannot be written when the NOTE P 0 ...
Page 74
... These read/write bits control the high byte of the modulo feedback divider that selects the VCO frequency multiplier N. (See LOCK 0 0 ACQ Reserved MUL11 5.3.3 PLL Circuits and 5.3.6 Programming the MC68HC908GP32 Data Sheet, Rev Bit Bit 0 MUL10 MUL9 MUL8 PLL.) A value of $0000 in Freescale Semiconductor ...
Page 75
... Figure 5-8. PLL VCO Range Select Register (PMRS) VRS7–VRS0 — VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with E (See 5.3.3 PLL Circuits, 5.3.6 Programming the hardware center-of-range frequency, f Freescale Semiconductor NOTE MUL6 MUL5 ...
Page 76
... Exceptions.) A value of $00 in the VCO range select Exceptions.). Reset initializes the register to NOTE NOTE RDS3 5.3.6 Programming the PLL.) RDS7–RDS0 cannot be written when the 5.3.7 Special Programming NOTE NOTE MC68HC908GP32 Data Sheet, Rev. 10 5.3.8 Base 2 1 Bit 0 RDS2 RDS1 RDS0 Exceptions.) Reset Freescale Semiconductor ...
Page 77
... To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. Freescale Semiconductor NOTE 14.7.3 SIM Break Flag Control MC68HC908GP32 Data Sheet, Rev ...
Page 78
... PLL. 78 5.3.3 PLL Circuits, Register.) 5.8.3 Choosing a . The power supply potential alters the DDA MC68HC908GP32 Data Sheet, Rev. 10 RDV and the XCLK 5.3.6 Programming the PLL, and Filter.) Freescale Semiconductor . ...
Page 79
... Either of the filter networks in Figure 5-10 Figure 5-10 (a) is used for applications requiring better stability. applications where stability is not critical. 0.033 µF Freescale Semiconductor Time, the external filter network is critical to the is recommended when using a 32.768kHz reference crystal. CGMXFC 10 kΩ 0.01 µF ...
Page 80
... Clock Generator Module (CGM) 80 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 81
... POR (power-on reset). The CONFIG registers are not in the FLASH memory but are special registers containing one-time writeable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Address: $001E Bit 7 Read: 0 Write: Reset Unimplemented Figure 6-1. Configuration Register 2 (CONFIG2) Freescale Semiconductor NOTE Figure 6 MC68HC908GP32 Data Sheet, Rev ...
Page 82
... LVIPWRD disables the LVI module. (See 1 = LVI module power disabled 0 = LVI module power enabled LVISTOP LVIRSTD LVIPWRD LVI5OR3 See Note subsection 3.5.2 Stop Mode.) Chapter 11 Low-Voltage Inhibit MC68HC908GP32 Data Sheet, Rev Bit 0 SSREC STOP COPD Chapter 7 Computer Operating Chapter 11 Low-Voltage Inhibit (LVI).) Freescale Semiconductor 3.5 (LVI).) ...
Page 83
... STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. (See 1 = COP module disabled 0 = COP module enabled Freescale Semiconductor NOTE NOTE Chapter 7 Computer Operating Properly MC68HC908GP32 Data Sheet, Rev. 10 Functional Description Chapter 11 Low-Voltage Inhibit ...
Page 84
... Configuration Register (CONFIG) 84 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 85
... COPCTL WRITE COPEN (FROM SIM) COP DISABLE (FROM CONFIG) RESET COPCTL WRITE COP RATE SEL (FROM CONFIG) Freescale Semiconductor 12-BIT COP PRESCALER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER Figure 7-1. COP Block Diagram MC68HC908GP32 Data Sheet, Rev. 10 ...
Page 86
... A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 86 NOTE NOTE Figure 7-1. 7.4 COP Control MC68HC908GP32 Data Sheet, Rev During the break state, TST Register) clears the COP Freescale Semiconductor ...
Page 87
... Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. Freescale Semiconductor (CONFIG).) (CONFIG).) 6 ...
Page 88
... STOP instruction. When the STOP bit in the configuration register has the STOP instruction is disabled, execution of a STOP instruction results in an illegal opcode reset. 7.8 COP Module During Break Mode The COP is disabled during a break interrupt when present on the RST pin. TST MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 89
... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 8.3 CPU Registers Figure 8-1 shows the five CPU registers. CPU registers are not part of the memory map. Freescale Semiconductor MC68HC908GP32 Data Sheet, Rev ...
Page 90
... CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 8-1. CPU Registers Unaffected by reset Figure 8-2. Accumulator ( Figure 8-3. Index Register (H:X) MC68HC908GP32 Data Sheet, Rev Bit 0 Bit Freescale Semiconductor ...
Page 91
... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: Freescale Semiconductor ...
Page 92
... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result NOTE MC68HC908GP32 Data Sheet, Rev Bit Freescale Semiconductor ...
Page 93
... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. Freescale Semiconductor MC68HC908GP32 Data Sheet, Rev. 10 Arithmetic/Logic Unit (ALU) ...
Page 94
... REL 27 rr – – – – – – REL – – – – – – REL 28 rr – – – – – – REL 29 rr – – – – – – REL 22 rr Freescale Semiconductor ...
Page 95
... Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? IRQ = 1 PC ← (PC rel ? IRQ = 0 (A) & (M) ⊕ PC ← (PC rel ? ( – – – – – – REL PC ← ...
Page 96
... SP1 9E6A ff – – – – ↕ ↕ INH 52 IMM A8 ii DIR B8 dd EXT IX2 – – ↕ ↕ – IX1 SP1 9EE8 ff SP2 9ED8 ee ff DIR 3C dd INH 4C INH 5C ↕ – – ↕ ↕ – IX1 SP1 9E6C ff Freescale Semiconductor ...
Page 97
... ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack Freescale Semiconductor Description PC ← Jump Address PC ← (PC Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – ← Unconditional Address A ← (M) H:X ← (M ← (M) ...
Page 98
... INH 8E DIR BF dd EXT IX2 – – ↕ ↕ – IX1 SP1 9EEF ff SP2 9EDF ee ff IMM A0 ii DIR B0 dd EXT IX2 ↕ – – ↕ ↕ ↕ IX1 SP1 9EE0 ff SP2 9ED0 ee ff Freescale Semiconductor ...
Page 99
... M Memory location N Negative bit 8.8 Opcode Map See Table 8-2. Freescale Semiconductor Description PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...
Page 100
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
Page 101
... IRQ module. RESET ACK IRQ VECTOR FETCH DECODER V DD INTERNAL PULLUP DEVICE IRQ Freescale Semiconductor V DD CLR IRQ LATCH IMASK MODE NOTE: On FLASH devices, high-voltage disables FLASH block protection. Figure 9-1. IRQ Module Block Diagram MC68HC908GP32 Data Sheet, Rev. 10 ...
Page 102
... When using the level-sensitive interrupt trigger, avoid false IRQ interrupts by masking interrupt requests in the interrupt routine. 9.3.2 MODE = 0 If MODE is clear, the IRQ pin is falling edge sensitive only. With MODE clear, an IRQ vector fetch or software clear immediately clears the IRQ latch. 102 NOTE NOTE MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 103
... The IRQ module does not share its pin with any module on this MCU. 9.7.1 IRQ Input Pins (IRQ) The IRQ pin provides a maskable external interrupt source. The IRQ pin contains an internal pullup device. Freescale Semiconductor sheet. MC68HC908GP32 Data Sheet, Rev. 10 Interrupts ...
Page 104
... MODE — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin IRQ interrupt request on falling edges and low levels 0 = IRQ interrupt request on falling edges only 104 IRQF MC68HC908GP32 Data Sheet, Rev Bit 0 0 IMASK MODE ACK Freescale Semiconductor ...
Page 105
... The keyboard interrupt module controls the enabling/disabling of interrupt functions on the KBI pins. These pins can be enabled/disabled independently of each other. INTERNAL BUS VECTOR FETCH DECODER ACKK RESET KBI0 KBIE0 KBIx KBIEx Figure 10-1. Keyboard Interrupt Block Diagram Freescale Semiconductor V DD CLR KBI LATCH MODEK MC68HC908GP32 Data Sheet, Rev. 10 KEYF SYNCHRONIZER ...
Page 106
... IMASKK, which makes it useful in applications where polling is preferred. Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin input, overriding the data direction register. However, the data direction register bit must for software to read the pin. 106 NOTE MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 107
... If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. Freescale Semiconductor sheet. MC68HC908GP32 Data Sheet, Rev. 10 ...
Page 108
... MODEK — Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only 108 KEYF MC68HC908GP32 Data Sheet, Rev Bit 0 0 IMASKK MODEK ACKK Freescale Semiconductor ...
Page 109
... Figure 10-3. Keyboard Interrupt Enable Register (INTKBIER) KBIE7–KBIE0 — Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin to latch KBI interrupt requests KBIx pin enabled as keyboard interrupt pin 0 = KBIx pin not enabled as keyboard interrupt pin Freescale Semiconductor KBIE5 ...
Page 110
... Keyboard Interrupt (KBI) Module 110 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 111
... The LVI in this case will hold the part in reset until either V DD release reset or V the power-on reset and reset the trip point to 3-V operation. Freescale Semiconductor voltage falls below the LVI trip falling voltage voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI falls below a voltage configured for 5-V operation ...
Page 112
... V DD TRIPF to remain above the V level, enabling LVI resets allows the LVI TRIPF falls below the V level. In the configuration register, the DD TRIPF MC68HC908GP32 Data Sheet, Rev. 10 LVISTOP FROM CONFIG1 LVI RESET level, software can monitor V DD Freescale Semiconductor 6.2 Bit polling ...
Page 113
... This read-only flag becomes set when the V (See Table 11-1.) Reset clears the LVIOUT bit. V 11.5 LVI Interrupts The LVI module does not generate interrupt requests. Freescale Semiconductor fall below V ), the LVI will maintain a reset condition until DD TRIPF . This prevents a condition in which the MCU is TRIPR ...
Page 114
... MCU out of wait mode. 11.6.2 Stop Mode If enabled in stop mode (LVISTOP set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. 114 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 115
... Reset: Read: Port B Data Register $0001 Write: (PTB) Reset: Read: Port C Data Register $0002 Write: (PTC) Reset: Read: Port D Data Register $0003 Write: (PTD) Reset: Freescale Semiconductor Bit PTA7 PTA6 PTA5 PTB7 PTB6 PTB5 0 PTC6 PTC5 PTD7 PTD6 PTD5 = Unimplemented Figure 12-1 ...
Page 116
... PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0 Unimplemented MC68HC908GP32 Data Sheet, Rev Bit 0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC3 DDRC2 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 PTE1 PTE0 0 0 DDRE1 DDRE0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 Freescale Semiconductor ...
Page 117
... Freescale Semiconductor DDR Module Control DDRA0 KBIE0 DDRA1 KBIE1 DDRA2 KBIE2 DDRA3 KBIE3 KBD DDRA4 KBIE4 DDRA5 KBIE5 DDRA6 KBIE6 DDRA7 KBIE7 DDRB0 DDRB1 DDRB2 DDRB3 ADC ADCH4–ADCH0 DDRB4 DDRB5 DDRB6 DDRB7 DDRC0 DDRC1 DDRC2 DDRC3 DDRC4 DDRC5 DDRC6 DDRD0 ...
Page 118
... Unaffected by reset KBD6 KBD5 KBD4 KBD3 Figure 12-2. Port A Data Register (PTA) (see Chapter 10 Keyboard Interrupt (KBI DDRA6 DDRA5 DDRA4 DDRA3 NOTE MC68HC908GP32 Data Sheet, Rev Bit 0 PTA3 PTA2 PTA1 PTA0 KBD2 KBD1 KBD0 2 1 Bit 0 DDRA2 DDRA1 DDRA0 Freescale Semiconductor Module) ...
Page 119
... DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRA is configured for output mode. Address: $000D Bit 7 Read: PTAPUE7 Write: Reset: 0 Figure 12-5. Port A Input Pullup Enable Register (PTAPUE) Freescale Semiconductor DDRAx RESET PTAx V DD INTERNAL PULLUP DEVICE Figure 12-4. Port A I/O Circuit Table 12-2 summarizes the operation of the port A pins ...
Page 120
... Figure 12-7. Data Direction Register B (DDRB) 120 PTB6 PTB5 PTB4 Unaffected by reset AD6 AD5 AD4 Figure 12-6. Port B Data Register (PTB) NOTE DDRB6 DDRB5 DDRB4 DDRB3 MC68HC908GP32 Data Sheet, Rev Bit 0 PTB3 PTB2 PTB1 PTB0 AD3 AD2 AD1 AD0 2 1 Bit 0 DDRB2 DDRB1 DDRB0 Freescale Semiconductor ...
Page 121
... Notes Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. Freescale Semiconductor NOTE DDRBx RESET PTBx Figure 12-8. Port B I/O Circuit Table 12-3 summarizes the operation of the port B pins. Table 12-3. Port B Pin Functions Accesses to DDRB ...
Page 122
... Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 122 NOTE PTC6 PTC5 PTC4 PTC3 Unaffected by reset Figure 12-9. Port C Data Register (PTC DDRC6 DDRC5 DDRC4 DDRC3 NOTE MC68HC908GP32 Data Sheet, Rev Bit 0 PTC2 PTC1 PTC0 2 1 Bit 0 DDRC2 DDRC1 DDRC0 Freescale Semiconductor ...
Page 123
... Notes Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. 4. I/O pin pulled internal pullup device. DD Freescale Semiconductor NOTE DDRCx RESET PTCx V DD INTERNAL PULLUP DEVICE Figure 12-11. Port C I/O Circuit Table 12-4 summarizes the operation of the port C pins. ...
Page 124
... I/O pins or general-purpose I/O pins. See 124 PTCPUE5 PTCPUE4 PTCPUE3 NOTE PTD6 PTD5 PTD4 PTD3 Unaffected by reset T2CH0 T1CH1 T1CH0 SPSCK Chapter 17 Timer Interface Module MC68HC908GP32 Data Sheet, Rev Bit 0 PTCPUE2 PTCPUE1 PTCPUE0 Bit 0 PTD2 PTD1 PTD0 MOSI MISO SS (TIM). Freescale Semiconductor ...
Page 125
... These read/write bits control port D data direction. Reset clears DDRD7–DDRD0, configuring all port D pins as inputs Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from Freescale Semiconductor Chapter 17 Timer Interface Module Table 12- ...
Page 126
... Table 12-5. Port D Pin Functions Accesses to DDRD I/O Pin Mode Read/Write (4) (1) DDRD7–DDRD0 Input (2) X DDRD7–DDRD0 Input, Hi-Z X Output DDRD7–DDRD0 MC68HC908GP32 Data Sheet, Rev. 10 PTDx Accesses to PTD Read Write (3) Pin PTD7–PTD0 (3) Pin PTD7–PTD0 PTD7–PTD0 PTD7–PTD0 Freescale Semiconductor ...
Page 127
... E. Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the SCI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. See Freescale Semiconductor ...
Page 128
... Figure 12-19 shows the port E I/O logic. READ DDRE ($000C) WRITE DDRE ($000C) WRITE PTE ($0008) READ PTE ($0008) 128 (SCI). (SCI NOTE DDREx RESET PTEx Figure 12-19. Port E I/O Circuit MC68HC908GP32 Data Sheet, Rev Bit 0 0 DDRE1 DDRE0 PTEx Freescale Semiconductor ...
Page 129
... X Input, Hi Notes Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. Freescale Semiconductor Table 12-6 summarizes the operation of the port E pins. Table 12-6. Port E Pin Functions Accesses to DDRE Read/Write (2) DDRE1–DDRE0 Output DDRE1–DDRE0 MC68HC908GP32 Data Sheet, Rev ...
Page 130
... Input/Output (I/O) Ports 130 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 131
... Configuration register bit, SCIBDSRC, to allow selection of baud rate clock source 13.3 Pin Name Conventions The generic names of the SCI I/O pins are: • RxD (receive data) • TxD (transmit data) Freescale Semiconductor MC68HC908GP32 Data Sheet, Rev. 10 131 ...
Page 132
... The baud rate clock source for the SCI can be selected via the configuration bit, SCIBDSRC, of the CONFIG2 register ($001E). Source selection values are shown in 132 Table 13-1 Table 13-1. Pin Name Conventions RxD PTE1/RxD MC68HC908GP32 Data Sheet, Rev. 10 shows the full names and the generic TxD PTE0/TxD Figure 13-1. Freescale Semiconductor ...
Page 133
... SBK IDLE WAKEUP CONTROL SCIBDSRC FROM ENSCI CONFIG2 SL CGMXCLK A ÷ SCALER BUS CLOCK => SCICLK = CGMXCLK => SCICLK = BUS CLOCK Freescale Semiconductor INTERNAL BUS LOOPS RECEIVE FLAG CONTROL CONTROL BKF RPF PRE- BAUD DIVIDER DATA SELECTION ÷16 Figure 13-1. SCI Module Block Diagram MC68HC908GP32 Data Sheet, Rev ...
Page 134
... ILIE TE RE RWU ORIE NEIE FEIE IDLE BKF SCP0 R SCR2 SCR1 Reserved U = Unaffected Figure 13-3. PARITY NEXT BIT START STOP BIT BIT 7 BIT PARITY NEXT BIT START BIT 7 BIT 8 STOP BIT BIT Freescale Semiconductor Bit 0 PTY 0 SBK 0 PEIE RPF SCR0 0 ...
Page 135
... Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8). Freescale Semiconductor 13-4. INTERNAL BUS BAUD ÷ ...
Page 136
... May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits 13.4.2.4 Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. 136 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 137
... SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request. Freescale Semiconductor NOTE 1.) MC68HC908GP32 Data Sheet, Rev ...
Page 138
... SCR2 SCR1 SCR0 PRE- BAUD ÷ 16 DIVIDER DATA PTE1/RxD RECOVERY ALL 0s M WAKEUP LOGIC PARITY CHECKING OR ORIE NF NEIE FE FEIE PE PEIE MC68HC908GP32 Data Sheet, Rev. 10 SCI DATA REGISTER 11-BIT RECEIVE SHIFT REGISTER SCRF IDLE R8 OR ORIE NF NEIE FE FEIE PE PEIE Freescale Semiconductor RWU ...
Page 139
... RT3, RT5, and RT7 Start bit verification is not successful if any two of the three verification samples are logic 1s. If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. Freescale Semiconductor 13-6): START BIT START BIT ...
Page 140
... Data Bit Samples Determination 000 0 001 0 010 0 011 1 100 0 101 1 110 1 111 1 NOTE Table 13-4. Stop Bit Recovery Framing Samples Error Flag 000 1 001 1 010 1 011 0 100 1 101 0 110 0 111 0 MC68HC908GP32 Data Sheet, Rev. 10 Noise Flag Table 13-4 Noise Flag Freescale Semiconductor ...
Page 141
... With the misaligned character shown in the count of the transmitting device is 10 bit times × cycles + 3 RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is Freescale Semiconductor MSB STOP DATA SAMPLES Figure 13-7 ...
Page 142
... Figure 13-8, the receiver counts 154 RT cycles at the point when ˙ 154 160 – × 100 = 3.90% ------------------------- - 154 Figure 13-8, the receiver counts 170 RT cycles at the point when 170 176 – × 100 = 3.53% ------------------------- - 170 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 143
... Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt requests. Freescale Semiconductor NOTE MC68HC908GP32 Data Sheet, Rev. 10 Functional Description ...
Page 144
... The PTE0/TxD pin is the serial data output from the SCI transmitter. The SCI shares the PTE0/TxD pin with port E. When the SCI is enabled, the PTE0/TxD pin is an output regardless of the state of the DDRE2 bit in data direction register E (DDRE). 144 for information on exiting wait mode. for information on exiting stop mode. MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 145
... ENSCI — Enable SCI Bit This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit SCI enabled 0 = SCI disabled Freescale Semiconductor ...
Page 146
... Odd parity 0 = Even parity Changing the PTY bit in the middle of a transmission or reception can generate a parity error. 146 NOTE Table 13-5.) When enabled, the parity function Figure NOTE MC68HC908GP32 Data Sheet, Rev. 10 Table 13-5.) 13-3.) Reset clears the PEN bit. Freescale Semiconductor ...
Page 147
... This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Reset clears the SCRIE bit SCRF enabled to generate CPU interrupt 0 = SCRF not enabled to generate CPU interrupt Freescale Semiconductor Table 13-5. Character Format Selection Character Format Start Bits Data Bits ...
Page 148
... Transmit break characters break characters being transmitted Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble. 148 NOTE NOTE NOTE MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 149
... PEIE — Receiver Parity Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the parity error bit, PE. (See 13.8.4 SCI Status Register 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled Freescale Semiconductor ...
Page 150
... IDLE generates an SCI receiver CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must 150 SCRF IDLE MC68HC908GP32 Data Sheet, Rev Bit Freescale Semiconductor ...
Page 151
... This clearable, read-only bit is set when the SCI detects noise on the PTE1/RxD pin. NF generates an SCI error CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset clears the NF bit Noise detected noise detected Freescale Semiconductor MC68HC908GP32 Data Sheet, Rev. 10 I/O Registers 151 ...
Page 152
... SCRF = READ SCDR BYTE 2 DELAYED FLAG CLEARING SEQUENCE BYTE 2 BYTE 3 READ SCS1 SCRF = READ SCDR BYTE 1 Figure 13-13. Flag Clearing Sequence MC68HC908GP32 Data Sheet, Rev. 10 BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 Freescale Semiconductor ...
Page 153
... Reading the SCDR accesses the read-only received data bits, R7:R0. Writing to the SCDR writes the data to be transmitted, T7:T0. Reset has no effect on the SCDR. Do not use read/modify/write instructions on the SCI data register. 13.8.7 SCI Baud Rate Register The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter. Freescale Semiconductor ...
Page 154
... Table 13-7. SCI Baud Rate Selection Baud Rate Divisor (BD) 000 001 010 011 100 101 110 111 × × MC68HC908GP32 Data Sheet, Rev Bit 0 SCR2 SCR1 SCR0 Reserved Table 13-6. Reset clears SCP1 Table 13-7. Reset clears 128 Freescale Semiconductor is BUS ...
Page 155
... Freescale Semiconductor SCR2, SCR1, Baud Rate and SCR0 Divisor (BD) 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 MC68HC908GP32 Data Sheet, Rev ...
Page 156
... Serial Communications Interface Module (SCI) 156 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 157
... Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal Freescale Semiconductor Figure 14-1. Table 14-1. Signal Name Conventions Description MC68HC908GP32 Data Sheet, Rev. 10 Table 14 summary of the SIM 157 ...
Page 158
... COP CLOCK CGMXCLK (FROM CGM) CGMOUT (FROM CGM) INTERNAL CLOCKS LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE SBSW Note 0 ILOP ILAD MODRST LVI Reserved Freescale Semiconductor Bit ...
Page 159
... The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in come from either an external oscillator or from the on-chip PLL. (See (CGM).) OSC2 OSCILLATOR (OSC) OSC1 OSCSTOPENB FROM CONFIG CGMRCLK PHASE-LOCKED LOOP (PLL) Freescale Semiconductor Bit BCFE IF6 IF5 ...
Page 160
... Reset Recovery Type POR/LVI All others 160 14.6.2 Stop 14.4 SIM Counter), but an external reset does not. Each of shows the relative timing. Table 14-2. Reset Recovery Type Actual Number of Cycles 4163 (4096 + ( MC68HC908GP32 Data Sheet, Rev. 10 Mode.) 14.7 SIM Registers.) Freescale Semiconductor ...
Page 161
... The external reset pin (RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. Freescale Semiconductor Figure 14-4. External Reset Timing NOTE ...
Page 162
... The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. 162 32 32 CYCLES CYCLES Figure 14-7. POR Recovery on the RST pin disables the COP module. TST MC68HC908GP32 Data Sheet, Rev. 10 $FFFE $FFFF while the MCU is in monitor TST Freescale Semiconductor ...
Page 163
... SIM Counter and Reset States External reset has no effect on the SIM counter. (See free-running after all reset states. (See internal reset recovery sequences.) Freescale Semiconductor 14.6.2 Stop Mode 14.3.2 Active Resets from Internal Sources MC68HC908GP32 Data Sheet, Rev. 10 SIM Counter ...
Page 164
... SP – – – 1[15:8] . Figure 14-8 Interrupt Entry Timing SP – – – – 1 [15:8] PC – 1 [7:0] Figure 14-9. Interrupt Recovery Timing MC68HC908GP32 Data Sheet, Rev. 10 Figure 14-8 shows VECT H VECT L START ADDR CCR V DATA H V DATA L OPCODE OPCODE OPERAND Freescale Semiconductor ...
Page 165
... YES AS MANY INTERRUPTS AS EXIST ON CHIP Freescale Semiconductor FROM RESET BREAK YES I BIT SET? INTERRUPT BIT SET? NO YES IRQ INTERRUPT? NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES UNSTACK CPU REGISTERS INSTRUCTION? NO EXECUTE INSTRUCTION Figure 14-10 ...
Page 166
... A software interrupt pushes PC onto the stack. A software interrupt does not push PC – hardware interrupt does. 166 CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Interrupt Recognition Example NOTE NOTE MC68HC908GP32 Data Sheet, Rev. 10 BACKGROUND ROUTINE Freescale Semiconductor ...
Page 167
... Figure 14-12. Interrupt Status Register 1 (INT1) IF6–IF1 — Interrupt Flags 1–6 These flags indicate the presence of interrupt requests from the sources shown Interrupt request present interrupt request present Freescale Semiconductor Table 14-3. Interrupt Sources Interrupt Source Reset SWI instruction IRQ pin ...
Page 168
... IF13 IF12 IF11 IF10 Reserved Reserved Chapter 17 Timer Interface Module MC68HC908GP32 Data Sheet, Rev Bit 0 IF9 IF8 IF7 Table 14- Bit 0 0 IF16 IF15 Table 14-3. (TIM).) The SIM puts the CPU into the Freescale Semiconductor ...
Page 169
... IAB WAIT ADDR IDB PREVIOUS DATA R/W Note: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Freescale Semiconductor WAIT ADDR + 1 SAME NEXT OPCODE Figure 14-15. Wait Mode Entry Timing MC68HC908GP32 Data Sheet, Rev. 10 Low-Power Modes Figure 14-15 ...
Page 170
... External crystal applications should use the full stop recovery time by clearing the SSREC bit unless the OSCSTOPEN bit is set in CONFIG2. 170 show the timing for WAIT recovery. $6E0B $6E0C $00FF $00FE $A6 $A6 $01 $ CYCLES CYCLES $A6 NOTE MC68HC908GP32 Data Sheet, Rev. 10 $00FD $00FC $6E RST VCT H RST VCT L Freescale Semiconductor ...
Page 171
... STOP +1 Figure 14-19. Stop Mode Recovery from Interrupt or Break 14.7 SIM Registers The SIM has three memory-mapped registers. Address $FE00 $FE01 $FE03 Freescale Semiconductor Figure 14-18 NOTE STOP ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 14-18. Stop Mode Entry Timing STOP RECOVERY PERIOD ...
Page 172
... Last reset caused by external reset pin (RST POR or read of SRSR COP — Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR 172 Reserved PIN COP ILOP ILAD MC68HC908GP32 Data Sheet, Rev Bit 0 SBSW R R Note Bit 0 MODRST LVI Freescale Semiconductor ...
Page 173
... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Freescale Semiconductor ...
Page 174
... System Integration Module (SIM) 174 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 175
... I/O pins with four parallel I/O ports. The full names of the SPI I/O pins are shown in follows. SPI Generic Pin Names: Full SPI SPI Pin Names: Freescale Semiconductor Table 15-1. The generic pin names appear in the text that Table 15-1. Pin Name Conventions MISO MOSI SS PTD1/MISO ...
Page 176
... Register.) NOTE 15.13.1 SPI Control Figure 15-3.) Register.) Through the SPSCK pin, the baud rate generator of the MC68HC908GP32 Data Sheet, Rev. 10 shows the structure of the SPI module CPOL CPHA SPWOM SPE SPTE MODFEN SPR1 Reserved Register.) Freescale Semiconductor Bit 0 SPTIE 0 SPR0 ...
Page 177
... CLOCK SPMSTR SPE SELECT SPR1 TRANSMITTER CPU INTERRUPT REQUEST RECEIVER/ERROR CPU INTERRUPT REQUEST MASTER MCU SHIFT REGISTER BAUD RATE GENERATOR Figure 15-3. Full-Duplex Master-Slave Connections Freescale Semiconductor INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER RECEIVE DATA REGISTER SPR0 SPMSTR ...
Page 178
... Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing the SPI enable bit (SPE). 178 15.5 Transmission NOTE NOTE MC68HC908GP32 Data Sheet, Rev. 10 15.7.2 Mode Fault Error.) Formats.) Freescale Semiconductor ...
Page 179
... Therefore, the SPI data register of the slave must be loaded with transmit data before the falling edge of SS. Any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission. Freescale Semiconductor 15.7.2 Mode Fault 1 ...
Page 180
... SPI clock is free-running uncertain where the write to the SPDR occurs relative to the slower 180 MSB BIT 6 BIT 5 BIT 4 BIT 3 MSB BIT 6 BIT 5 BIT 4 BIT 3 Figure 15-7.) The internal SPI clock in the master is a free-running MC68HC908GP32 Data Sheet, Rev BIT 2 BIT 1 LSB BIT 2 BIT 1 LSB Freescale Semiconductor ...
Page 181
... The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready Freescale Semiconductor INITIATION DELAY MSB ...
Page 182
... BYTE 3 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 11 CPU READS SPSCR WITH SPRF BIT SET. 12 CPU READS SPDR, CLEARING SPRF BIT. MC68HC908GP32 Data Sheet, Rev. 10 Figure 15-8 shows 10 BIT BIT BIT BIT LSB MSB BIT BIT BIT BYTE Freescale Semiconductor ...
Page 183
... OVRF interrupt or do another read of the SPSCR following the read of the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions can set the SPRF bit. SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit. Freescale Semiconductor Figure 15-4 and Figure ...
Page 184
... TO CHECK OVRF BIT. 10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 11 BYTE 4 SETS SPRF BIT. 12 CPU READS SPSCR. 13 CPU READS BYTE 4 IN SPDR, CLEARING SPRF BIT. 14 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. MC68HC908GP32 Data Sheet, Rev. 10 BYTE Figure 15-11.) Freescale Semiconductor ...
Page 185
... Four SPI status flags can be enabled to generate CPU interrupt requests. Flag SPTE Transmitter empty SPRF Receiver full OVRF Overflow MODF Mode fault Freescale Semiconductor NOTE 15.5 Transmission NOTE NOTE Table 15-2. SPI Interrupts Request SPI transmitter CPU interrupt request (SPTIE = 1, SPE = 1) SPI receiver CPU interrupt request ...
Page 186
... If the SPI transmit interrupt enable bit, SPTIE, is also set, SPTE generates an SPTE CPU interrupt request. 186 Figure 15-11.) SPTE SPTIE SPE SPRIE SPRF MC68HC908GP32 Data Sheet, Rev. 10 SPI TRANSMITTER CPU INTERRUPT REQUEST SPI RECEIVER/ERROR CPU INTERRUPT REQUEST Freescale Semiconductor ...
Page 187
... The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See Freescale Semiconductor 15.8 Chapter 14 System Integration Module MC68HC908GP32 Data Sheet, Rev ...
Page 188
... MCUs exchange a byte of data in eight serial clock cycles. When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I/O port. 188 ) SS MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 189
... Note Don’t care 15.12.5 CGND (Clock Ground) CGND is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers internally connected shown in SS Freescale Semiconductor Figure 15-12. BYTE 1 BYTE 2 Figure 15-12. CPHA/SS Timing 15.13.2 SPI Status and Control NOTE 15 ...
Page 190
... SPWOM — SPI Wired-OR Mode Bit This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins become open-drain outputs. 190 SPMSTR CPOL CPHA Reserved MC68HC908GP32 Data Sheet, Rev Bit 0 SPWOM SPE SPTIE Figure Figure Freescale Semiconductor ...
Page 191
... ERRIE — Error Interrupt Enable Bit This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears the ERRIE bit MODF and OVRF can generate CPU interrupt requests 0 = MODF and OVRF cannot generate CPU interrupt requests Freescale Semiconductor ...
Page 192
... For an enabled SPI configured as a slave, having MODFEN low only prevents the MODF flag from being set. It does not affect any other part of SPI operation. (See Fault Error.) 192 NOTE Select).) MC68HC908GP32 Data Sheet, Rev. 10 15.7.2 Mode Freescale Semiconductor ...
Page 193
... Address: $0012 Bit 7 Read: R7 Write: T7 Reset: R7–R0/T7–T0 — Receive/Transmit Data Bits Do not use read-modify-write instructions on the SPI data register since the register read is not the same as the register written. Freescale Semiconductor Baud Rate Divisor (BD) BUSCLK = ----------------------- - × Figure ...
Page 194
... Serial Peripheral Interface Module (SPI) 194 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 195
... If the TBIE bit is set, an interrupt request is sent to the CPU. The TBIF flag is cleared by writing the TACK bit. The first time the TBIF flag is set after enabling the timebase module, the interrupt is generated at approximately half of the overflow period. Subsequent events occur at the exact period. Freescale Semiconductor NOTE MC68HC908GP32 Data Sheet, Rev. 10 ...
Page 196
... Figure 16-1. Timebase Block Diagram TBR2 TBR1 TBR0 TACK Unimplemented R MC68HC908GP32 Data Sheet, Rev. 10 TBON ÷ 128 TBMINT TBIF SEL Bit 0 TBIE TBON Reserved Freescale Semiconductor TBIE ...
Page 197
... TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt request. Interrupts must be acknowledged by writing a logic 1 to the TACK bit. Freescale Semiconductor Timebase Interrupt Rate TBR0 ...
Page 198
... If the oscillator has not been enabled to operate in stop mode, the timebase module will not be active during STOP mode. In stop mode the timebase register is not accessible by the CPU. If the timebase functions are not required during stop mode, reduce the power consumption by stopping the timebase before enabling the STOP instruction. 198 MC68HC908GP32 Data Sheet, Rev. 10 Freescale Semiconductor ...
Page 199
... References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TCH0 may refer generically to T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1. Freescale Semiconductor Table 17-1. The generic pin names appear in the text that follows. ...
Page 200
... ELS0B ELS0A CH0F MS0A MS0B ELS1B ELS1A CH1F MS1A Figure 17-1. TIM Block Diagram NOTE MC68HC908GP32 Data Sheet, Rev. 10 TOF INTERRUPT LOGIC TOIE TOV0 PORT CH0MAX T[1,2]CH0 LOGIC INTERRUPT LOGIC CH0IE TOV1 PORT CH1MAX T[1,2]CH1 LOGIC INTERRUPT LOGIC CH1IE Freescale Semiconductor ...