MC68HC908RF2MFA Freescale Semiconductor, MC68HC908RF2MFA Datasheet

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MC68HC908RF2MFA

Manufacturer Part Number
MC68HC908RF2MFA
Description
IC MCU 2K FLASH 4MHZ 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908RF2MFA

Core Processor
HC08
Core Size
8-Bit
Speed
4MHz
Peripherals
LVD, POR, PWM, RF Mod
Number Of I /o
12
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-

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Price
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MC68HC908RF2MFA
Manufacturer:
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MC68HC908RF2MFA
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Freescale Semiconductor, Inc.
MC68HC908RF2
Data Sheet
M68HC08
Microcontrollers
MC68HC908RF2/D
Rev. 4
5/2004
MOTOROLA.COM/SEMICONDUCTORS
For More Information On This Product,
Go to: www.freescale.com

Related parts for MC68HC908RF2MFA

MC68HC908RF2MFA Summary of contents

Page 1

... Freescale Semiconductor, Inc. M68HC08 Microcontrollers MOTOROLA.COM/SEMICONDUCTORS For More Information On This Product, Go to: www.freescale.com MC68HC908RF2 Data Sheet MC68HC908RF2/D Rev. 4 5/2004 ...

Page 2

... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

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... Freescale Semiconductor, Inc. MC68HC908RF2 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://motorola.com/semiconductors The following revision history table summarizes changes contained in this document ...

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... Freescale Semiconductor, Inc. Revision History Revision Date Level First bulleted paragraph under the subsection 11.5 Interrupts reworded for clarity Revision to the description of the CHxMAX bit and the note that follows that description 14.2 Absolute Maximum Ratings — ESD HBM and ESD MM entries added June, 14.8 UHF Transmitter Module — ...

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... Freescale Semiconductor, Inc. Data Sheet — MC68HC908RF2 Section 1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Section 3. Configuration Register (CONFIG Section 4. Computer Operating Properly Module (COP Section 5. Central Processor Unit (CPU Section 6. Internal Clock Generator Module (ICG Section 7. Keyboard/External Interrupt Module (KBI Section 8. Low-Voltage Inhibit (LVI 103 Section 9 ...

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... Freescale Semiconductor, Inc. List of Sections Data Sheet 6 For More Information On This Product, List of Sections Go to: www.freescale.com MC68HC908RF2 — Rev. 4.0 MOTOROLA ...

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... Freescale Semiconductor, Inc. Data Sheet — MC68HC908RF2 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2 Input/Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4 Random-Access Memory (RAM 2.5 FLASH 2TS Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2 ...

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... Freescale Semiconductor, Inc. Table of Contents 2.5.9 2.5.9.1 2.5.9.2 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Section 4. Computer Operating Properly Module (COP) 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4 ...

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... Freescale Semiconductor, Inc. 5.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.1 6.3.2 6.3.2.1 6.3.2.2 6.3.2.3 6.3.2.4 6.3.3 6.3.3.1 6.3.3.2 6.3.4 6.3.4.1 6.3.4.2 6.3.4.3 6.3.5 6.3.5.1 6.3.5.2 6.4 Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6 ...

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... Freescale Semiconductor, Inc. Table of Contents 6.6 Configuration Register Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.6.1 6.7 I/O Registers 6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.4.1 7.4.2 7.5 I/O Registers 101 7.5.1 7 ...

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... Freescale Semiconductor, Inc. 9.3 Port 110 9.3.1 9.3.2 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . 115 10.2.1 10.2.2 10.2.3 10.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.3.1 10.3.2 10.3.2.1 10.3.2.2 10.3.2.3 10.3.2.4 10.3.2.5 10.4 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.4.1 10.4.2 10 ...

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... Freescale Semiconductor, Inc. Table of Contents 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.4.6 11.4.7 11.4.8 11.4.9 11.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 11.5.1 11.5.2 11.5.3 11.6 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 11.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 11.7.1 11.7.2 11.8 I/O Registers 139 11.8.1 11 ...

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... Freescale Semiconductor, Inc. 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 13.2 Break Module (BRK 157 13.2.1 13.2.1.1 13.2.1.2 13.2.1.3 13.2.1.4 13.2.2 13.2.2.1 13.2.2.2 13.2.3 13.2.3.1 13.2.3.2 13.3 Monitor Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 13.3.1 13.3.1.1 13.3.1.2 13.3.1.3 13.3.1.4 13.3.1.5 13.3.1.6 13.3.2 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14 ...

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... Freescale Semiconductor, Inc. Table of Contents 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.3 32-Pin LQFP Package (Case No. 873A 186 Data Sheet 14 For More Information On This Product, Section 15. Ordering Information and Mechanical Specifications Table of Contents Go to: www.freescale.com MC68HC908RF2 — Rev. 4.0 MOTOROLA ...

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... Freescale Semiconductor, Inc. Data Sheet — MC68HC908RF2 1.1 Introduction The MC68HC908RF2 MCU is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). Optimized for low-power operation and available in a small 32-pin low-profile quad flat pack (LQFP), this MCU is well suited for remote keyless entry (RKE) transmitter designs. ...

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... Freescale Semiconductor, Inc. General Description • 12 general-purpose input/output (I/O) ports: – – – • Low-voltage inhibit (LVI) module: – – • 6-bit keyboard interrupt with wakeup feature • External asynchronous interrupt pin with internal pullup (IRQ) • Ultra high frequency (UHF) transmitter • ...

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... Freescale Semiconductor, Inc. M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 32 BYTES USER FLASH — 2031 BYTES USER RAM — 128 BYTES MONITOR ROM — 768 BYTES USER FLASH VECTOR SPACE — 14 BYTES SOFTWARE SELECTABLE OSC2 INTERNAL OSCILLATOR ...

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... Freescale Semiconductor, Inc. General Description 1.4 Pin Assignments Figure 1-2 1.4.1 Power Supply Pins ( and V DD single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as shown in as close to the MCU power pins as possible ...

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... Freescale Semiconductor, Inc. 1.4.2 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the connections to an external clock source or crystal/ceramic resonator. 1.4.3 External Reset (RST) A logic 0 on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system driven low when any internal reset source is asserted ...

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... Freescale Semiconductor, Inc. General Description 1.4.7 UHF Transmitter Pins The MC68HC908RF2 uses dedicated pins for its UHF module. These pins are described in Pin Data Sheet 20 For More Information On This Product, Table 1-1. Table 1-1. UHF Transmitter Pins Function 6 GND Ground 7 XTAL1 ...

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... Freescale Semiconductor, Inc. Data Sheet — MC68HC908RF2 2.1 Introduction The memory map, shown in • 2031 bytes of user FLASH memory • 128 bytes of random-access memory (RAM) • 14 bytes of user-defined vectors in FLASH memory • 768 bytes of monitor read-only memory (ROM) These definitions apply to the memory map representation of reserved and unimplemented locations: • ...

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... Freescale Semiconductor, Inc. Memory Data Sheet 22 For More Information On This Product, $0000 I/O REGISTERS ↓ (28 BYTES) $003F $0040 UNIMPLEMENTED ↓ (64 BYTES) $007F $0080 RAM ↓ (128 BYTES) $00FF $0100 UNIMPLEMENTED ↓ (30,464 BYTES) $77FF $7800 FLASH MEMORY ↓ (2031 BYTES) $7FEE ...

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... Freescale Semiconductor, Inc. Addr. Register Name Read: Port A Data Register $0000 (PTA) Write: See page 108. Reset: Read: Port B Data Register $0001 (PTB) Write: See page 110. Reset: $0002 ↓ Unimplemented $0003 Read: Data Direction Register A $0004 (DDRA) Write: See page 109. ...

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... Freescale Semiconductor, Inc. Memory Addr. Register Name IRQ and Keyboard Status Read: and Control Register Write: $001A (INTKBSCR) Reset: See page 101. Read: Keyboard Interrupt Enable $001B Register (INTKBIER) Write: See page 102. Reset: $001C ↓ Unimplemented $001E Read: Configuration Register ...

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... Freescale Semiconductor, Inc. Addr. Register Name Read: Timer Channel 1 Status and $0028 Control Register (TSC1) Write: See page 143. Reset: Read: Timer Channel 1 Register $0029 High (TCH1H) Write: See page 146. Reset: Read: Timer Channel 1 Register $002A Low (TCH1L) Write: See page 146. ...

Page 26

... Freescale Semiconductor, Inc. Memory Addr. Register Name Read: SIM Reset Status Register $FE01 (SRSR) Write: See page 127. POR: Read: SIM Break Flag Control $FE02 Register (SBFCR) Write: See page 128. Reset: $FE03 ↓ Reserved $FE04 $FE05 ↓ Unimplemented $FE07 Read: ...

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... Freescale Semiconductor, Inc. Addr. Register Name FLASH 2TS Block Protect Read: Register (FLBPR) † Write: $FFF0 See page 34. Reset: † Non-volatile FLASH register Read: COP Control Register $FFFF (COPCTL) Write: See page 49. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Table 2-1 2 ...

Page 28

... Freescale Semiconductor, Inc. Memory 2.4 Random-Access Memory (RAM) Addresses $0080–$00FF are RAM locations. The location of the stack RAM is programmable. NOTE: For correct operation, the stack pointer must point only to RAM locations. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers ...

Page 29

... Freescale Semiconductor, Inc. Program and erase operations are facilitated through control bits in a memory mapped register. Details for these operations appear later in this section. Memory in the FLASH 2TS array is organized into pages within rows. For the 2-Kbyte array on the MC68HC908RF2, the page size is one byte. There are eight pages (or eight bytes) per row ...

Page 30

... Freescale Semiconductor, Inc. Memory BLK0 — Block Erase Control Bit This read/write bit together with BLK1 allows erasing of blocks of varying size. See 2.5.3 FLASH 2TS Erase Operation sizes. HVEN — High-Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array ...

Page 31

... Freescale Semiconductor, Inc. 2.5.3 FLASH 2TS Erase Operation Use this step-by-step procedure to erase a block of FLASH 2TS memory. Refer to 14.12 Memory Characteristics algorithm. 1. Set the ERASE, BLK0, BLK1, and FDIV0 bits in the FLASH 2TS control register. Refer to sizes. 2. Ensure target portion of array is unprotected by reading the block protect register at address $FFF0 ...

Page 32

... Freescale Semiconductor, Inc. Memory 2.5.4 FLASH 2TS Program/Margin Read Operation NOTE: After a total of eight program operations have been applied to a row, the row must be erased before further programming to avoid program disturb. An erased byte will read $00. The FLASH 2TS memory is programmed on a page basis. A page consists of one byte ...

Page 33

... Freescale Semiconductor, Inc. Page Program/Margin Read Procedure Note: This algorithm is mandatory for programming the FLASH 2TS. Note: This page program algorithm assumes the page programmed are initially erased. Figure 2-4. Smart Programming Algorithm Flowchart MC68HC908RF2 — Rev. 4.0 MOTOROLA For More Information On This Product, ...

Page 34

... Freescale Semiconductor, Inc. Memory 2.5.5 FLASH 2TS Block Protection NOTE: In performing a program or erase operation, the FLASH 2TS block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit. Due to the ability of the on-board charge pump to erase and program the FLASH ...

Page 35

... Freescale Semiconductor, Inc. BPR2 — Block Protect Register Bit 2 This bit protects the memory contents in the address ranges $7900–$7FEF and $FFF0–$FFFF Address range protected from erase or program 0 = Address range open to erase or program BPR1 — Block Protect Register Bit 1 This bit protects the memory contents in the address ranges $7880– ...

Page 36

... Freescale Semiconductor, Inc. Memory The functions shown in global variables in RAM. passing parameters. Table 2-5. Embedded FLASH Routine Global Variables 1. RAMSTART is defined as the starting address of the RAM in the memory map. 2.5.8 Embedded Function Descriptions This subsection describes the embedded functions. 2.5.8.1 RDVRRNG Routine ...

Page 37

... Freescale Semiconductor, Inc. 2.5.8.2 PRGRNGE Routine Name: PRGRNGE Purpose: Programs a range of addresses in FLASH memory Entry conditions: H:X LADDR DATA CPUSPD BUMPS Exit conditions: C bit I bit This routine programs a range of FLASH defined by H:X and LADDR. The range can be from one byte to as much RAM as can be allocated to DATA. The smart ...

Page 38

... Freescale Semiconductor, Inc. Memory This routine erases the block of FLASH defined by H:X and CTLBYTE. The algorithm defined in Preserves the contents of H:X (address passed) 2.5.8.4 REDPROG Routine Name: REDPROG Purpose: This routine will use a range of multiple rows in the FLASH array to emulate increased write/erase cycling capability of one row. ...

Page 39

... Freescale Semiconductor, Inc. The row whose cycling bit is different will be erased and the entire row will be programmed with the given data, including a toggled version of the cycling bit. 2.5.8.5 Example Routine Calls This code is for illustrative purposes only and does not represent valid syntax for any particular assembler ...

Page 40

... Freescale Semiconductor, Inc. Memory LDHX #$7800 JSR ERARNGE ;************************************************************; ; CALLING EXAMPLE FOR PROGRAM A RANGE (RNGEPROG) ;************************************************************* MOV #’P’,DATA MOV #’R’,DATA+1 MOV #’O’,DATA+2 MOV #’G’,DATA+3 MOV #’T’,DATA+4 MOV #’E’,DATA+5 MOV #’S’,DATA+6 MOV #’ ...

Page 41

... Freescale Semiconductor, Inc. 2.5.9 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 2.5.9.1 Wait Mode Putting the MCU into wait mode while the FLASH 2TS is in read mode does not affect the operation of the FLASH 2TS memory directly, but there will be no memory activity since the CPU is inactive ...

Page 42

... Freescale Semiconductor, Inc. Memory Data Sheet 42 For More Information On This Product, Memory Go to: www.freescale.com MC68HC908RF2 — Rev. 4.0 MOTOROLA ...

Page 43

... Freescale Semiconductor, Inc. Data Sheet — MC68HC908RF2 3.1 Introduction This section describes the configuration register (CONFIG). The configuration register enables or disables these options: • Stop mode recovery time (32 CGMXCLK cycles or 4,096 CGMXCLK cycles) • COP timeout period (2 • STOP instruction • ...

Page 44

... Freescale Semiconductor, Inc. Configuration Register (CONFIG) frequency higher (307.2 kHz–32 MHz) or lower (60 Hz–307.2 kHz) than the base frequency of the internal oscillator. (See Generator Module 1 = ICG set for slow external crystal operation 0 = ICG set for fast external crystal operation LVISTOP — LVI Enable in Stop Mode Bit When the LVIPWR bit is set, setting the LVISTOP bit enables the LVI to operate during stop mode ...

Page 45

... Freescale Semiconductor, Inc. STOP — STOP Instruction Enable Bit STOP enables the STOP instruction STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. (See Properly Module 1 = COP module disabled 0 = COP module enabled MC68HC908RF2 — ...

Page 46

... Freescale Semiconductor, Inc. Configuration Register (CONFIG) Data Sheet 46 For More Information On This Product, Configuration Register (CONFIG) Go to: www.freescale.com MC68HC908RF2 — Rev. 4.0 MOTOROLA ...

Page 47

... Freescale Semiconductor, Inc. Data Sheet — MC68HC908RF2 Section 4. Computer Operating Properly Module (COP) 4.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by periodically clearing the COP counter ...

Page 48

... Freescale Semiconductor, Inc. Computer Operating Properly Module (COP) The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 2 state of the COP rate select bit, COPRS, in the configuration register. When COPRS = ...

Page 49

... Freescale Semiconductor, Inc. 4.3.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 4.3.7 COPD The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. (See 4 ...

Page 50

... Freescale Semiconductor, Inc. Computer Operating Properly Module (COP) 4.7.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. ...

Page 51

... Freescale Semiconductor, Inc. Data Sheet — MC68HC908RF2 5.1 Contents The M68HC08 CPU (central processor unit enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. ...

Page 52

... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 5.3 CPU Registers Figure 5-1 map. 5.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: Write: Reset: Data Sheet 52 For More Information On This Product, shows the five CPU registers ...

Page 53

... Freescale Semiconductor, Inc. 5.3.2 Index Register The 16-bit index register allows indexed addressing of a 64-Kbyte memory space the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand ...

Page 54

... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 5.3.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location ...

Page 55

... Freescale Semiconductor, Inc. H — Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor ...

Page 56

... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 5.4 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU ...

Page 57

... Freescale Semiconductor, Inc. 5.7 Instruction Set Summary Table 5-1 Table 5-1. Instruction Set Summary (Sheet Source Operation Form ADC #opr ADC opr ADC opr ADC opr,X Add with Carry ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ...

Page 58

... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 5-1. Instruction Set Summary (Sheet Source Operation Form Branch if Greater Than or Equal To BGE opr (Signed Operands) Branch if Greater Than (Signed BGT opr Operands) BHCC rel Branch if Half Carry Bit Clear BHCS rel Branch if Half Carry Bit Set ...

Page 59

... Freescale Semiconductor, Inc. Table 5-1. Instruction Set Summary (Sheet Source Operation Form BRSET n,opr,rel Branch if Bit Set BSET n,opr Set Bit BSR rel Branch to Subroutine CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel ...

Page 60

... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 5-1. Instruction Set Summary (Sheet Source Operation Form CPX #opr CPX opr CPX opr CPX ,X Compare X with M CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA Decimal Adjust A DBNZ opr,rel DBNZA rel DBNZX rel ...

Page 61

... Freescale Semiconductor, Inc. Table 5-1. Instruction Set Summary (Sheet Source Operation Form LDHX #opr Load H:X from M LDHX opr LDX #opr LDX opr LDX opr LDX opr,X Load X from M LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX Logical Shift Left ...

Page 62

... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 5-1. Instruction Set Summary (Sheet Source Operation Form ROL opr ROLA ROLX Rotate Left through Carry ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX Rotate Right through Carry ROR opr,X ROR ,X ROR opr,SP ...

Page 63

... Freescale Semiconductor, Inc. Table 5-1. Instruction Set Summary (Sheet Source Operation Form SWI Software Interrupt TAP Transfer A to CCR TAX Transfer TPA Transfer CCR to A TST opr TSTA TSTX Test for Negative or Zero TST opr,X TST ,X TST opr,SP TSX Transfer SP to H:X ...

Page 64

... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Data Sheet 64 For More Information On This Product, Central Processor Unit (CPU) Go to: www.freescale.com MC68HC908RF2 — Rev. 4.0 MOTOROLA ...

Page 65

... Freescale Semiconductor, Inc. Data Sheet — MC68HC908RF2 6.1 Introduction The internal clock generator module (ICG) is used to create a stable clock source for the microcontroller without using any external components. The ICG generates the oscillator output clock (CGMXCLK), which is used by the COP, LVI, and other modules ...

Page 66

... Freescale Semiconductor, Inc. Internal Clock Generator Module (ICG) CS RESET CMON N[6:0] TRIM[7:0] SIMOSCEN ECGON ICGON EXTSLOW INTERNAL TO MCU EXTERNAL NAME NAME Figure 6-1. ICG Module Block Diagram Data Sheet 66 For More Information On This Product, CLOCK SELECTION CIRCUIT CLOCK MONITOR/SWITCHER CIRCUIT INTERNAL CLOCK ...

Page 67

... Freescale Semiconductor, Inc. 6.3.1 Clock Enable Circuit The clock enable circuit is used to enable the internal clock (ICLK) or external clock (ECLK). The clock enable circuit generates an ICG stop (ICGSTOP) signal which stops all clocks (ICLK, ECLK, and the low-frequency base clock, IBASE) low. ...

Page 68

... Freescale Semiconductor, Inc. Internal Clock Generator Module (ICG) The internal clock generator contains: • A digitally controlled oscillator • A modulo N divider • A frequency comparator, which contains voltage and current references, a frequency to voltage converter, and comparators • A digital loop filter 6.3.2.1 Digitally Controlled Oscillator The digitally controlled oscillator (DCO inaccurate oscillator which generates the internal clock (ICLK) ...

Page 69

... Freescale Semiconductor, Inc. 6.3.2.4 Digital Loop Filter The digital loop filter (DLF) uses the outputs of the frequency comparator to adjust the internal clock (ICLK) clock period. The DLF generates the DCO divider control bits (DDIV[3:0]) and the DCO stage control bits (DSTG[7:0]), which are fed to the DCO ...

Page 70

... Freescale Semiconductor, Inc. Internal Clock Generator Module (ICG) 6.3.3 External Clock Generator The ICG also provides for an external oscillator or clock source, if desired. The external clock generator, shown in amplifier and an external clock input path. STOP ECGON EXTSLOW INTERNAL TO MCU EXTERNAL NAME CONFIGURATION REGISTER BIT ...

Page 71

... Freescale Semiconductor, Inc. The amplifier is enabled when the ECGON bit is set and stop mode is not enabled. When the amplifier is enabled, it will be connected between the OSC1 and OSC2 pins. In its typical configuration, the external oscillator requires five external components: 1. Crystal Fixed capacitor ...

Page 72

... Freescale Semiconductor, Inc. Internal Clock Generator Module (ICG) The clock monitor circuit, shown in • Clock monitor reference generator • Internal clock activity detector • External clock activity detector CMON IBASE ICGEN EXTSLOW STOP ECGON ECLK NAME NAME Figure 6-4. Clock Monitor Block Diagram 6 ...

Page 73

... Freescale Semiconductor, Inc. the low-frequency base clock (IBASE) is used in place of ICLK because it always operates at or near 307.2 kHz. For proper operation, EREF must be at least twice as slow as IBASE and IREF must be at least twice as slow as ECLK. To guarantee that IREF is slower than ECLK and EREF is slower than IBASE, one of the signals is divided down ...

Page 74

... Freescale Semiconductor, Inc. Internal Clock Generator Module (ICG) 6.3.4.2 Internal Clock Activity Detector The internal clock activity detector looks for at least one falling edge on the low-frequency base clock (IBASE) every time the external reference (EREF) is low. Since EREF is less than half the frequency of IBASE, this should occur every time. ...

Page 75

... Freescale Semiconductor, Inc. RESET NAME 6.3.5.2 Clock Switching Circuit To robustly switch between the internal clock (ICLK) and the external clock (ECLK), the switch assumes the clocks are completely asynchronous synchronizing circuit is required to make the transition (see is changed, the switch will continue to operate off the original clock for between 1 and 2 cycles as the select input transitions through one side of the synchronizer ...

Page 76

... Freescale Semiconductor, Inc. Internal Clock Generator Module (ICG) The switch automatically selects ICLK during reset. When the clock monitor is on (CMON is set) and it determines one of the clock sources is inactive (as indicated by the IOFF or EOFF signals), the circuit is forced to select the active clock. There are no clocks for the inactive side of the synchronizer to properly operate, so that side is forced deselected ...

Page 77

... Freescale Semiconductor, Inc. ;Clock Switching Code Example ;This code switches from Internal to External clock ;Clock Monitor and interrupts are not enabled start lda #$13 ;Mask for CS, ECGON, ECGS ;If switching from External to Internal, mask is $0C. loop ** ** ;Other code here, such as writing the COP, since ECGS may ...

Page 78

... Freescale Semiconductor, Inc. Internal Clock Generator Module (ICG) 6.4.3 Clock Monitor Interrupts The clock monitor circuit can be used to recover from perilous situations such as crystal loss. To use the clock monitor effectively, these notes should be observed: • Enable the clock monitor and clock monitor interrupts. ...

Page 79

... Freescale Semiconductor, Inc. DDIV[3:0] %0000 (min) %0000 (min) %0101–%1001 (max) 6.4.4.2 Binary Weighted Divider The binary weighted divider divides the output of the ring oscillator by a power of 2, specified by the DCO divider control bits (DDIV[3:0]). DDIV maximizes at %1001 (values of %1010 through %1111 are interpreted as %1001), which corresponds to a divide by 512. When DDIV is %0000, the ring oscillator’ ...

Page 80

... Freescale Semiconductor, Inc. Internal Clock Generator Module (ICG) Likewise, when DSTG[4:0] is %11111, the ring operates at 25 stage delays for cycles and at 23 stage delays for one of 32 cycles. When DSTG[7:5] is %111, similar results are achieved by including a variable divide-by-two, so the ring operates at 31 stages for some cycles and at 17 stage delays, with a divide-by-two for an effective 34 stage delays, for the remainder of the cycles ...

Page 81

... Freescale Semiconductor, Inc. 6.4.6 Nominal Frequency Settling Time Because the clock period of the internal clock (ICLK) is dependent on the digital loop filter outputs (DDIV and DSTG) which cannot change instantaneously, ICLK will temporarily operate at an incorrect clock period when any of the operating condition changes ...

Page 82

... Freescale Semiconductor, Inc. Internal Clock Generator Module (ICG) 6.4.6.2 Settling to Within 5 Percent Once the clock period is within 15 percent of the desired clock period, the filter starts making smaller adjustments. When between 15 percent and 5 percent error, each correction will adjust the clock period between 1.61 percent and 2.94 percent. ...

Page 83

... Freescale Semiconductor, Inc. 6.4.7 Improving Settling Time The settling time of the internal clock generator can be vastly improved if an external clock source can be used during the settling time. When the internal clock generator is disabled (ICGON is low), the DDIV[3:0] and DSTG[7:0] bits can be written ...

Page 84

... Freescale Semiconductor, Inc. Internal Clock Generator Module (ICG) ;DDIV and DSTG modification code example ;Changes DDIV and DSTG according to the initial and ; desired clock period values ;Requires ICGON to be clear (disabled) ;User must previously calculate DVFACT and STFACT by ; the equations listed in the specification ...

Page 85

... Freescale Semiconductor, Inc. The method of changing the unadjusted operating point is by changing the size of the capacitor. This capacitor is designed with 639 equally sized units, 384 of which are always connected. The remaining 255 units are put in by adjusting the ICG trim factor (TRIM). The default value for TRIM is $80, or 128 units, making the default capacitor size 512. Each unit added or removed will adjust the output frequency by about ± ...

Page 86

... Freescale Semiconductor, Inc. Internal Clock Generator Module (ICG) 6.6 Configuration Register Option One configuration register option affects the functionality of the ICG: EXTSLOW (slow external clock). All configuration register options will have a default setting. Refer to Configuration Register (CONFIG) 6.6.1 EXTSLOW Slow external clock (EXTSLOW), when set, will decrease the drive strength of the oscillator amplifier, enabling low-frequency crystal operation (30 kHz– ...

Page 87

... Freescale Semiconductor, Inc. Addr. Register Name Read: Internal Clock Generator $0038 Trim Register (ICGTR) Write: See page 90. Reset: Read: ICG DCO Divider Control $0039 Register (ICGDVR) Write: See page 91. Reset: Read: ICG DCO Stage Register Write: $003A (ICGDSR) See page 91. ...

Page 88

... Freescale Semiconductor, Inc. Internal Clock Generator Module (ICG) 6.7.1 ICG Control Register The ICG control register (ICGCR) contains the control and status bits for the internal clock generator, external clock generator, and clock monitor as well as the clock select and interrupt enable bits. ...

Page 89

... Freescale Semiconductor, Inc. CS — Clock Select Bit This read/write bit determines which clock will generate the oscillator output clock (CGMXCLK). This bit can be set when ECGON and ECGS have been set for at least one bus cycle and can be cleared when ICGON and ICGS have been set for at least one bus cycle ...

Page 90

... Freescale Semiconductor, Inc. Internal Clock Generator Module (ICG) 6.7.2 ICG Multiplier Register Address: $0037 Read: Write: Reset: N6–N0 — ICG Multiplier Factor Bits These read/write bits change the multiplier used by the internal clock generator. The internal clock (ICLK) will be (307.2 kHz ±25 percent value of $00 in this register is interpreted the same as a value of $01 ...

Page 91

... Freescale Semiconductor, Inc. 6.7.4 ICG DCO Divider Register Address: $0039 Read: Write: Reset: DDIV3–DDIV0 — ICG DCO Divider Control Bits These bits indicate the number of divide-by-twos (DDIV) that follow the digitally controlled oscillator. Incrementing DDIV will add another divide-by-two, doubling the period (halving the frequency). Decrementing has the opposite effect ...

Page 92

... Freescale Semiconductor, Inc. Internal Clock Generator Module (ICG) Data Sheet 92 For More Information On This Product, Internal Clock Generator Module (ICG) Go to: www.freescale.com MC68HC908RF2 — Rev. 4.0 MOTOROLA ...

Page 93

... Freescale Semiconductor, Inc. Data Sheet — MC68HC908RF2 7.1 Introduction This section describes the maskable external interrupt (IRQ) input and six independently maskable keyboard wakeup interrupt pins. 7.2 Features Features of the KBI include: • Dedicated external interrupt pin (IRQ) • Six keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask • ...

Page 94

... Freescale Semiconductor, Inc. Keyboard/External Interrupt Module (KBI) M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 32 BYTES USER FLASH — 2031 BYTES USER RAM — 128 BYTES MONITOR ROM — 768 BYTES USER FLASH VECTOR SPACE — 14 BYTES ...

Page 95

... Freescale Semiconductor, Inc. ACKI RESET VECTOR FETCH DECODER INTERNAL DD PULLUP DEVICE IRQ MODEI Addr. Register Name IRQ and Keyboard Status Read: and Control Register Write: $001A (INTKBSCR) Reset: See page 101. Read: Keyboard Interrupt Enable $001B Register (INTKBIER) Write: See page 102. ...

Page 96

... Freescale Semiconductor, Inc. Keyboard/External Interrupt Module (KBI) The IRQ1 pin and keyboard interrupt pins are falling-edge triggered and are software-configurable to be both falling-edge and low-level triggered. The MODEI and MODEK bits in the INTKBSCR controls the triggering sensitivity of the IRQ pin and keyboard interrupt pins. ...

Page 97

... Freescale Semiconductor, Inc. If the MODEI bit is clear, the IRQ pin is falling-edge sensitive only. With MODEI clear, a vector fetch or software clear immediately clears the IRQ1 latch.The IRQ1F bit in the INTKBSCR register can be used to check for pending interrupts. The IRQ1F bit is not affected by the IMASKI bit, which makes it useful in applications where polling is preferred ...

Page 98

... Freescale Semiconductor, Inc. Keyboard/External Interrupt Module (KBI) KBD1 . TO PULLUP ENABLE . KB1IE . KBD6 TO PULLUP ENABLE KB6IE Figure 7-5. Keyboard Interrupt Block Diagram 7.3.3 KBI Module During Break Interrupts The system integration module (SIM) controls whether the IRQ1 or keyboard interrupt latches can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during the break state ...

Page 99

... Freescale Semiconductor, Inc. An IRQ1/keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. • If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low ...

Page 100

... Freescale Semiconductor, Inc. Keyboard/External Interrupt Module (KBI) NOTE: Setting a keyboard interrupt enable bit (KBIE<x>) forces the corresponding keyboard interrupt pin input, overriding the data direction register. However, the data direction register bit must for software to read the pin. 7.3.5 Keyboard Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1 ...

Page 101

... Freescale Semiconductor, Inc. 7.5 I/O Registers These registers control and monitor operation of the keyboard/external interrupt module: • IRQ and keyboard status and control register, INTKBSCR • Keyboard interrupt enable register, KBIER 7.5.1 IRQ and Keyboard Status and Control Register The IRQ and keyboard status and control register (INTKBSCR) controls and monitors operation of the keyboard/external interrupt module ...

Page 102

... Freescale Semiconductor, Inc. Keyboard/External Interrupt Module (KBI) KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit Keyboard interrupt pending keyboard interrupt pending ACKK — Keyboard Acknowledge Bit Writing this write-only bit clears the keyboard interrupt request. ACKK always reads as 0. Reset clears ACKK. IMASKK — ...

Page 103

... Freescale Semiconductor, Inc. Data Sheet — MC68HC908RF2 8.1 Introduction The low-voltage inhibit (LVI) module monitors the voltage on the V set a low voltage sense bit when V LVI will force a reset when the V 8.2 Features Features of the LVI module include: • Two levels of low-voltage condition are detected: – ...

Page 104

... Freescale Semiconductor, Inc. Low-Voltage Inhibit (LVI) In addition to forcing a reset condition, the LVI module has a second circuit dedicated to low-voltage detection. When V low-voltage comparator asserts the LOWV flag in the LVI status register (LVISR). In applications that require detecting low batteries, software can monitor by polling the LOWV bit ...

Page 105

... Freescale Semiconductor, Inc. 8.4 LVI Status Register The LVI status register flags V Address: $FE0F Read: Write: Reset: LVIOUT — LVI Output Bit The read-only flag becomes set when the V voltage for CGMXCLK cycles. Reset clears the LVIOUT bit. LOWV— LVI Low Indicator Bit ...

Page 106

... Freescale Semiconductor, Inc. Low-Voltage Inhibit (LVI) Data Sheet 106 For More Information On This Product, Low-Voltage Inhibit (LVI) Go to: www.freescale.com MC68HC908RF2 — Rev. 4.0 MOTOROLA ...

Page 107

... Freescale Semiconductor, Inc. Data Sheet — MC68HC908RF2 9.1 Introduction Twelve bidirectional input/output (I/O) pins form two parallel ports in the 32-pin low-profile quad flat pack (LQFP). All I/O pins are programmable as inputs or outputs. Port A bits PTA6–PTA1 have keyboard wakeup interrupts and internal pullup resistors ...

Page 108

... Freescale Semiconductor, Inc. Input/Output (I/O) Ports 9.2 Port A Port 8-bit special function port that shares six of its pins with the keyboard interrupt module (KBD). PTA6–PTA1 contain pullup resistors enabled when the port pin is enabled as a keyboard interrupt. Port A pins are also high-current port pins with 3-mA sink capabilities ...

Page 109

... Freescale Semiconductor, Inc. 9.2.2 Data Direction Register A Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing DDRA bit enables the output buffer for the corresponding port A pin disables the output buffer. Address: Read: Write: Reset: DDRA[7:0] — Data Direction Register A Bits These read/write bits control port A data direction ...

Page 110

... Freescale Semiconductor, Inc. Input/Output (I/O) Ports (2) KBIE Bit Notes Don’t care 2. Keyboard interrupt enable bit (see 3. Writing affects data register, but does not affect input. 4. I/O pin pulled Hi-Z = High impedance NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin input, overriding the data direction register ...

Page 111

... Freescale Semiconductor, Inc. TCH0 — Timer Channel I/O Bit The PTB2/TCH0 pin is the TIM channel 0 input capture/output compare pin. The edge/level select bits, ELS0B:ELS0A, determine whether the PTB2/TCH0 pin is a timer channel I general-purpose I/O pin. See Interface Module TCLK — Timer Clock Bit The PTB3/TCLK pin is the external clock input for TIM ...

Page 112

... Freescale Semiconductor, Inc. Input/Output (I/O) Ports When bit DDRBx reading address $0001 reads the PTBx data latch. When bit DDRBx reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. ...

Page 113

... Freescale Semiconductor, Inc. Data Sheet — MC68HC908RF2 10.1 Introduction This section describes the system integration module (SIM). Together with the central processor unit (CPU), the SIM controls all MCU activities. The SIM is a system state controller that coordinates CPU and exception timing. ...

Page 114

... Freescale Semiconductor, Inc. System Integration Module (SIM) RESET PIN LOGIC RESET PIN CONTROL SIM RESET STATUS REGISTER Table 10-1 Signal Name CGMXCLK CGMOUT ICLK ECLK IAB IDB PORRST IRST R/W Data Sheet 114 For More Information On This Product, STOP/WAIT CONTROL SIM COUNTER ÷ ...

Page 115

... Freescale Semiconductor, Inc. 10.2 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in from the internal clock generator (ICG) module. ...

Page 116

... Freescale Semiconductor, Inc. System Integration Module (SIM) 10.3 Reset and System Initialization The MCU has these reset sources: • Power-on reset module (POR) • External reset pin (RST) • Computer operating properly module (COP) • Low-voltage inhibit module (LVI) • Illegal opcode • ...

Page 117

... Freescale Semiconductor, Inc. signal then follows the sequence from the falling edge of RST shown in 10-5. The COP reset is asynchronous to the bus clock. The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. ...

Page 118

... Freescale Semiconductor, Inc. System Integration Module (SIM) OSC1 PORRST 4096 CYCLES CGMXCLK CGMOUT RST IAB 10.3.2.2 Computer Operating Properly (COP) Reset The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR) if the COPD bit in the CONFIG register ...

Page 119

... Freescale Semiconductor, Inc. cycles later, the CPU is released from reset to allow the reset vector sequence to occur. (See 10.4 SIM Counter The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks ...

Page 120

... Freescale Semiconductor, Inc. System Integration Module (SIM) 10.5.1 Interrupts At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume ...

Page 121

... Freescale Semiconductor, Inc. BREAK INTERRUPT? YES AS MANY INTERRUPTS AS EXIST ON CHIP MC68HC908RF2 — Rev. 4.0 MOTOROLA For More Information On This Product, FROM RESET YES I BIT SET BIT SET? NO YES IRQ INTERRUPT? NO STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION YES ...

Page 122

... Freescale Semiconductor, Inc. System Integration Module (SIM) 10.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing ...

Page 123

... Freescale Semiconductor, Inc. 10.5.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC – hardware interrupt does. ...

Page 124

... Freescale Semiconductor, Inc. System Integration Module (SIM) 10.6.1 Wait Mode In wait mode, the CPU clocks are inactive while one set of peripheral clocks continues to run. A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred ...

Page 125

... Freescale Semiconductor, Inc. IAB IDB RST CGMXCLK 10.6.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode ...

Page 126

... Freescale Semiconductor, Inc. System Integration Module (SIM) CGMXCLK INT/BREAK IAB STOP +1 Figure 10-16. Stop Mode Recovery from Interrupt or Break 10.7 SIM Registers The SIM has three memory mapped registers: • SIM break status register, SBSR • SIM reset status register, SRSR • ...

Page 127

... Freescale Semiconductor, Inc. 10.7.2 SIM Reset Status Register This register contains six flags that show the source of the last reset. The status register will clear automatically after reading it. A power-on reset sets the POR bit. Address: Read: Write: POR: POR — Power-On Reset Bit ...

Page 128

... Freescale Semiconductor, Inc. System Integration Module (SIM) 10.7.3 SIM Break Flag Control Register The SIM break control register contains a bit that enables software to clear status bits while the MCU break state. Address: Read: Write: Reset: BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU break state ...

Page 129

... Freescale Semiconductor, Inc. Data Sheet — MC68HC908RF2 11.1 Introduction This section describes the timer interface module (TIM). The TIM is a 2-channel timer: • The first channel, channel 0, provides a timing reference with input capture, output compare, and pulse-width-modulation (PWM) functions. • The second channel, channel 1, provides reduced functionality as it doesn’t have an external pin ...

Page 130

... Freescale Semiconductor, Inc. Timer Interface Module (TIM) M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 32 BYTES USER FLASH — 2031 BYTES USER RAM — 128 BYTES MONITOR ROM — 768 BYTES USER FLASH VECTOR SPACE — 14 BYTES ...

Page 131

... Freescale Semiconductor, Inc. 11.4 Functional Description Figure 11-2 the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH and TMODL, control the modulo value of the TIM counter ...

Page 132

... Freescale Semiconductor, Inc. Timer Interface Module (TIM) Addr. Register Name Read: Timer Status and Control $0020 Register (TSC) Write: See page 139. Reset: Read: Timer Counter Register High $0021 (TCNTH) Write: See page 141. Reset: Read: Timer Counter Register Low $0022 ...

Page 133

... Freescale Semiconductor, Inc. 11.4.1 TIM Counter Prescaler The TIM clock source can be one of the seven prescaler outputs or the TIM clock pin, TCLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register select the TIM clock source ...

Page 134

... Freescale Semiconductor, Inc. Timer Interface Module (TIM) • When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period ...

Page 135

... Freescale Semiconductor, Inc. PTB2/TCH0 The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50 percent. 11.4.7 Unbuffered PWM Signal Generation ...

Page 136

... Freescale Semiconductor, Inc. Timer Interface Module (TIM) 11.4.8 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1 ...

Page 137

... Freescale Semiconductor, Inc. signal generation when changing the PWM pulse width to a new, much larger value the TIM status control register (TSC), clear the TIM stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H and TCH0L) initially control the buffered PWM output ...

Page 138

... Freescale Semiconductor, Inc. Timer Interface Module (TIM) 11.5.3 Stop Mode The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt. ...

Page 139

... Freescale Semiconductor, Inc. 11.7.2 TIM Channel I/O Pins (TCH0) The channel I/O pins are programmable independently as an input capture pin or an output compare pin. TCH0 can be configured as buffered output compare or buffered PWM pins. 11.8 I/O Registers These I/O registers control and monitor operation of the TIM: • ...

Page 140

... Freescale Semiconductor, Inc. Timer Interface Module (TIM) TOIE — TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled TSTOP — TIM Stop Bit This read/write bit stops the TIM counter ...

Page 141

... Freescale Semiconductor, Inc. 11.8.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read ...

Page 142

... Freescale Semiconductor, Inc. Timer Interface Module (TIM) 11.8.3 TIM Counter Modulo Registers The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. ...

Page 143

... Freescale Semiconductor, Inc. Register Name and Address: TSC0—$0025 Read: Write: Reset: Register Name and Address: TSC1—$0028 Read: Write: Reset: Figure 11-8. TIM Channel Status and Control Registers (TSC0 and TSC1) CHxF — Channel x Flag Bit When channel input capture channel, this read/write bit is set when an active edge occurs on the channel x pin ...

Page 144

... Freescale Semiconductor, Inc. Timer Interface Module (TIM) When ELSxB:A = 00, this read/write bit selects the initial output level of the TCH0 pin. See 1 = Initial output level low 0 = Initial output level high NOTE: Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC) ...

Page 145

... Freescale Semiconductor, Inc. NOTE: The state of TOV1 has no effect since there is no pin. When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time. Channel 1 should not be configured in input capture mode. WARNING: The user must configure TIM channel mode other than input capture recommended that this procedure be part of the initialization of the system after reset ...

Page 146

... Freescale Semiconductor, Inc. Timer Interface Module (TIM) Register Name and Address: TCH0H—$0026 Read: Write: Reset: Register Name and Address: TCH0L—$0027 Read: Write: Reset: Figure 11-10. TIM Channel 0 Registers (TCH0H and TCH0L) Register Name and Address: TCH1H—$0029 ...

Page 147

... Freescale Semiconductor, Inc. Data Sheet — MC68HC908RF2 12.1 Introduction This section describes the integrated radio frequency (RF) module. This module integrates an ultra high frequency (UHF) transmitter offering these key features: • Switchable frequency bands: 315, 434, and 868 MHz • On/off keying (OOK) and frequency shift keying (FSK) modulation • ...

Page 148

... Freescale Semiconductor, Inc. PLL Tuned UHF Transmitter Module M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 32 BYTES USER FLASH — 2031 BYTES USER RAM — 128 BYTES MONITOR ROM — 768 BYTES USER FLASH VECTOR SPACE — 14 BYTES ...

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... Freescale Semiconductor, Inc. 12.2 Transmitter Functional Description The transmitter is a phase-locked loop (PLL) tuned low-power UHF transmitter. The different modes of operation are controlled by the microcontroller through several digital input pins. The power supply voltage ranges from 1 3.7 V allowing operation with a single lithium cell. ...

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... Freescale Semiconductor, Inc. PLL Tuned UHF Transmitter Module 12.5 Modulation If a low-logic level is applied on pin MODE, then the on/off keying (OOK) modulation is selected. This modulation is performed by switching on/off the RF output stage. The logic level applied on pin DATA controls the output stage state: DATA = 0 → ...

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... Freescale Semiconductor, Inc. 12.7 State Machine Figure 12-3 ENABLE = 0 MC68HC908RF2 — Rev. 4.0 MOTOROLA For More Information On This Product, details the main state machine. POWER ON AND ENABLE = 0 STATE 1 STANDBY MODE ENABLE = 1 STATE 2 PLL ENABLED BUT OUT OF LOCK-IN RANGE PLL IN LOCK-IN RANGE ...

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... Freescale Semiconductor, Inc. PLL Tuned UHF Transmitter Module State 1 The circuit is in standby mode and draws only a leakage current from the power supply. State 2 In this state, the PLL is enabled but out of the lock-in range. Therefore the RF output stage is switched off preventing any data transmission. Data clock is available on pin DATACLK ...

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... Freescale Semiconductor, Inc. 12.8 Power Management When the battery voltage falls below the shutdown voltage threshold (V whole circuit is switched off. NOTE: After this shutdown, the circuit is latched until a low level is applied on pin ENABLE (see state 6 under 12.9 Data Clock When the data clock starts, the high-to-low ratio may be uneven. Similarly the clock is switched off asynchronously so the last period length is not guaranteed ...

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... Freescale Semiconductor, Inc. PLL Tuned UHF Transmitter Module Component Data Sheet 154 For More Information On This Product, TO MCU DATACLK MODE DATA ENABLE BAND V CC GND GNDRF XTAL1 RFOUT XTAL0 CFSK EXT R2 Figure 12-6. Application Schematic in FSK Modulation, 315-MHz and 434-MHz Frequency Bands Table 12-3 ...

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... Freescale Semiconductor, Inc. A example of crystal reference is: Tokyo Denpa TTS-3B 13568.750 kHz, see 12-4. Load capacitance Motional capacitance Static capacitance Loss resistance Carrier Frequency 12.10.2 Complete Application Schematic Figure 12-7 MC68HC908RF2. OOK modulation is selected, f MC68HC908RF2 — Rev. 4.0 MOTOROLA For More Information On This Product, Table 12-4 ...

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... Freescale Semiconductor, Inc. PLL Tuned UHF Transmitter Module ENABLE DATA C10 13.56 MHz Figure 12-7. Complete Application Schematic in OOK Modulation, Data Sheet 156 For More Information On This Product, SW1 SW2 PTA1/KBD1 1 PTA0 2 PTB0/MCLK 3 PTB1 4 MC68HC908RF2 PTB2/TCH0 5 GND 6 XTAL1 7 XTAL0 BATT C9 2.2 pF ...

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... Freescale Semiconductor, Inc. Data Sheet — MC68HC908RF2 13.1 Introduction This section describes the break module, the monitor module (MON), and the monitor mode entry methods. 13.2 Break Module (BRK) The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program ...

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... Freescale Semiconductor, Inc. Development Support IAB[15:0] Addr. Register Name Read: Break Address Register High $FE0C (BRKH) Write: See page 161. Reset: Read: Break Address Register Low $FE0D (BRKL) Write: See page 161. Reset: Read: Break Status and Control $FE0E Register (BSCR) Write: See page 160 ...

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... Freescale Semiconductor, Inc. 13.2.1.1 Flag Protection During Break Interrupts The system integration module (SIM) controls whether module status bits can be cleared during the break state. The BCFE bit in the SIM break flag control register (BFCR) enables software to clear status bits during the break state. (See SIM Break Flag Control Register module ...

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... Freescale Semiconductor, Inc. Development Support 13.2.3 Break Module Registers These registers control and monitor operation of the break module: • Break status and control register, BSCR • Break address register high, BRKH • Break address register low, BRKL 13.2.3.1 Break Status and Control Register The break status and control register (BSCR) contains break module enable and status bits ...

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... Freescale Semiconductor, Inc. 13.2.3.2 Break Address Registers The break address registers contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Register Name and Address: BRKH — $FE0C Read: Write: Reset: Register Name and Address: BRKL — $FE0D ...

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... Freescale Semiconductor, Inc. Development Support 1 MC145407 + 10 µ µ DB- Data Sheet 162 For More Information On This Product µ 9.8304 MHz µ MC74HC125 Figure 13-5. Monitor Mode Circuit Development Support Go to: www.freescale.com V DD 68HC908RF2 10 kΩ RST 0.1 µ kΩ IRQ1 OSC1 X1 10 MΩ ...

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... Freescale Semiconductor, Inc. While simple monitor commands can access any memory address, the MC68HC908RF2 has a FLASH security feature to prevent external viewing of the contents of FLASH. Proper procedures must be followed to verify FLASH content. Access to the FLASH is denied to unauthorized users of customer-specified software (see In monitor mode, the MCU can execute host-computer code in RAM while all MCU pins except PTA0 retain normal operating mode functions ...

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... Freescale Semiconductor, Inc. Development Support Table 13-2 Modes User Monitor 1. If the high voltage (V its COP enable output. The COP is a mask option enabled or disabled by the COPD bit in the configuration register. See Module. 13.3.1.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format ...

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... Freescale Semiconductor, Inc. 13.3.1.3 Echoing As shown in byte back to the PTA0 pin for error checking. Any result of a command appears after the echo of the last byte of the command. SENT TO MONITOR READ 1 ECHO Notes Echo delay (2 bit times Data return delay (2 bit times Wait 1 bit time before sending next byte ...

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... Freescale Semiconductor, Inc. Development Support 13.3.1.5 Commands The monitor ROM firmware uses these commands: • READ (read memory) • WRITE (write memory) • IREAD (indexed read) • IWRITE (indexed write) • READSP (read stack pointer) • RUN (run user program) The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking ...

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... Freescale Semiconductor, Inc. Description Operand Data Returned Opcode SENT TO MONITOR READ ECHO Description Operand Data Returned Opcode FROM HOST WRITE ECHO Description Operand Data Returned Opcode MC68HC908RF2 — Rev. 4.0 MOTOROLA For More Information On This Product, Table 13-3. READ (Read Memory) Command ...

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... Freescale Semiconductor, Inc. Development Support Description Operand Data Returned Opcode A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. Description Operand Data Returned Opcode Description Operand Data Returned Opcode Data Sheet 168 For More Information On This Product, Table 13-6 ...

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... Freescale Semiconductor, Inc. The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can modify the stacked CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value ...

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... Freescale Semiconductor, Inc. Development Support IRQ SEE NOTE V DD 4096 + 32 CGMXCLK CYCLES RST Note: Any delay between rising IRQ and rising V FROM HOST PA0 256 CGMXCLK CYCLES ONE BIT TIME FROM MCU Notes Echo delay (2 bit times Data return delay (2 bit times Wait 1 bit time before sending next byte ...

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... Freescale Semiconductor, Inc. Data Sheet — MC68HC908RF2 14.1 Introduction This section contains electrical and timing specifications. 14.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to 14 ...

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... Freescale Semiconductor, Inc. Electrical Specifications 14.3 Functional Operating Range Operating temperature range Operating voltage range 1. Extended temperature range to be determined 14.4 Thermal Characteristics Thermal resistance LQFP (32 pin) I/O pin power dissipation Power dissipation (2) Constant Average junction temperature Maximum junction temperature 1. Power dissipation is a function of temperature. ...

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... Freescale Semiconductor, Inc. 14.5 1.8-Volt to 3.3-Volt DC Electrical Characteristics Excluding UHF Module (1) Characteristic Output high voltage (I = –1.2 mA) Load (I = –2.0 mA) Load Output low voltage (I = 1.2 mA) Load (I = 3.0 mA) Load (I = 3.0 mA) PTA7–PTA0 only Load Input high voltage, all ports, IRQ1, OSC1 Input low voltage, all ports, IRQ1, OSC1 ...

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... Freescale Semiconductor, Inc. Electrical Specifications 14.6 3.0-Volt DC Electrical Characteristics Excluding UHF Module (1) Characteristic Output high voltage (I = –2.0 mA) Load (I = –8.0 mA) Load Output low voltage (I = 2.0 mA) Load (I = 6.5 mA) Load (I = 5.0 mA) PTA7–PTA0 only Load Input high voltage, all ports, IRQ, OSC1 Input low voltage, all ports, IRQ, OSC1 ...

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... Freescale Semiconductor, Inc. 14.7 2.0-Volt DC Electrical Characteristics Excluding UHF Module (1) Characteristic Output high voltage (I = –1.2 mA) Load (I = –2.0 mA) Load Output low voltage (I = 1.2 mA) Load (I = 3.0 mA) Load (I = 3.0 mA) PTA7–PTA0 only Load Input high voltage, all ports, IRQ, OSC1 Input low voltage, all ports, IRQ, OSC1 ...

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... Freescale Semiconductor, Inc. Electrical Specifications 14.8 UHF Transmitter Module This subsection provides electrical specifications and timing definitions for the UHF transmitter module. 14.8.1 UHF Module Electrical Characteristics Unless otherwise specified: • • R EXT • Operating temperature range (T • RF output frequency: f • ...

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... Freescale Semiconductor, Inc. Parameter Test Conditions and Comments Supply voltage Shutdown voltage threshold RF Parameters (assuming a 50 Ω matching network connected to the D.U.T. output) R value EXT Output power Current and output power variation vs R value EXT Harmonic 2 level Harmonic 3 level Spurious level ± ...

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... Freescale Semiconductor, Inc. Electrical Specifications Parameter Test Conditions and Comments RF spectrum Phase noise PLL lock-in time, f Carrier t PLL_Lock_In XTAL1 input capacitance Crystal resistance Modulation depth Data rate Input low voltage Input high voltage Input hysteresis voltage Input current ENABLE pulldown resistor ...

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... Freescale Semiconductor, Inc. MC68HC908RF2 — Rev. 4.0 MOTOROLA For More Information On This Product, Resolution Resolution bandwidth: bandwidth: Figure 14-1. RF Spectrum at 434-MHz Frequency Band Displayed with a 5-MHz Span Figure 14-2. RF Spectrum at 434-MHz Frequency Band Displayed with a 50-MHz Span Electrical Specifications Go to: www.freescale.com ...

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... Freescale Semiconductor, Inc. Electrical Specifications 14.8.2 UHF Module Output Power Measurement The RF output levels given in the are measured whith a 50-Ω load directly connected to the pin RFOUT as shown in figure Figure the application. Data Sheet 180 For More Information On This Product, Figure 14-3. RF Spectrum at 434-MHz Frequency Band Displayed with a 1 ...

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... Freescale Semiconductor, Inc. The configuration shown in output power and harmonics rejection. Schematic in equivalent circuit of the pin RFOUT and impeder as well as the matching network components for 434-MHz frequency band. NOTE: Note that the impeder is moved to the load side to decrease its influence (similar to dc bias through the antenna) ...

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... Freescale Semiconductor, Inc. Electrical Specifications –2 –4 – Figure 14-6. Output Power at 434-MHz Frequency Band versus R 14.9 Control Timing Characteristic Bus operating frequency = 3.0 V ± 10 2.0 V ± 10 RESET pulse width low IRQ interrupt pulse width low (edge-triggered) IRQ interrupt pulse period ...

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... Freescale Semiconductor, Inc. 14.10 Internal Oscillator Characteristics (1) Characteristic Internal oscillator base frequency without trim Internal oscillator base frequency (2) (3) with trim (4) Internal oscillator multiplier (5) External clock option 3 V ± 10 ± Vdc Internal oscillator is selectable through software for a maximum frequency. Actual frequency will be multiplier (N) x base frequency ...

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... Freescale Semiconductor, Inc. Electrical Specifications 14.12 Memory Characteristics Characteristic RAM data retention voltage FLASH pages per row FLASH bytes per page FLASH read bus clock frequency FLASH charge pump clock frequency (See 2.5.2 FLASH 2TS Charge Pump Frequency Control) FLASH block/bulk erase time ...

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... This section contains ordering information for the MC68HC908RF2. In addition, package dimensions are given for the 32-pin low-profile quad flat pack (LQFP). 15.2 MC Order Numbers MC68HC908RF2CFA MC68HC908RF2MFA Low-profile quad flat pack (LQFP) MC68HC908RF2 — Rev. 4.0 MOTOROLA Ordering Information and Mechanical Specifications For More Information On This Product, Table 15-1 ...

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... Freescale Semiconductor, Inc. Ordering Information and Mechanical 15.3 32-Pin LQFP Package (Case No. 873A –T– DETAIL –AB– SEATING –AC– PLANE 0.10 (0.004 DETAIL AD Data Sheet 186 Ordering Information and Mechanical Specifications For More Information On This Product, 4X 0.20 (0.008) AB T–U ...

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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

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... Freescale Semiconductor, Inc. HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre ...

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