HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet

IC H8S MCU FLASH 256K 144-QFP

HD64F2676VFC33

Manufacturer Part Number
HD64F2676VFC33
Description
IC H8S MCU FLASH 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2676VFC33

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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To our customers,
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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Related parts for HD64F2676VFC33

HD64F2676VFC33 Summary of contents

Page 1

To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

Page 2

All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

Page 3

H8S/2678 Group, H8S/2678R Group, 16 H8S/2676 F-ZTAT Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should ...

Page 4

Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...

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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...

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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Main Revisions in This Edition 5. Contents 6. Overview 7. Description of Functional Modules • ...

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The H8S/2678 Group and H8S/2678R Group are microcomputers (MCU) made up of the H8S/2600 CPU employing Renesas’ original architecture as their cores, and the peripheral functions required to configure a system. The H8S/2600 CPU has an internal 32-bit configuration, sixteen ...

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In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. In order to understand the details of a register when its name is known Read the index that is the final part ...

Page 9

Main Revisions in This Edition Item Page All — 6.2 Input/Output Pins 124 Table 6.1 Pin Configuration 124 7.5.1 Transfer 288 Modes Table 7.4 DMAC Transfer Modes 289 Section 10 I/O Ports 428 to 432 Table 10.1 Port Functions 432 ...

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Item Page 10.2.4 Pin Functions 445 445 10.6.4 Pin Functions 471 471 10.7.4 Pin Functions 477 477 10.9.5 Port A Open 486 Drain Control Register (PAODR) 10.9.6 Port Function 486 Control Register 1 (PFCR1) Rev. 3.00 Mar 17, 2006 page ...

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Item Page 10.15.4 Pin 515 Functions 515 10.16.4 Pin 520 Functions 11.1 Features 523 Table 11.1 TPU Functions 11.3.9 Timer 558 Synchronous Register (TSYR) 15.3.9 Bit Rate 679 Generator (BRR) Table 15.2 Relationships between N Setting in BRR and Bit ...

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Item Page 17.4 Operation 769 19.12 Usage Notes 804 Figure 19.12 Power- On/Off Timing (H8S/2678Group) Section 20 Masked 810 ROM Rev. 3.00 Mar 17, 2006 page Revision (See Manual for Details) Description added [2] Set the DAOE0 ...

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Item Page 21.2.1 Connecting a 814 Crystal Resonator 21.2.2 External Clock 815 Input 24.6 Flash Memory 907, Characteristics 908 Table 24.13 Flash Memory Characteristics C. Package 919 Dimensions Figure C.1 Package Dimensions (FP-144H) Figure C.2 Package 920 Dimensions (FP-144G) Revision ...

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Rev. 3.00 Mar 17, 2006 page xii of l ...

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Section 1 Overview ............................................................................................................. 1.1 Features ............................................................................................................................. 1.2 Block Diagram .................................................................................................................. 1.3 Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Arrangement in Each Operating Mode.......................................................... 1.3.3 Pin Functions ....................................................................................................... 13 Section 2 CPU ...................................................................................................................... 21 2.1 Features ............................................................................................................................. 21 2.1.1 ...

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Memory Indirect—@@aa:8 ................................................................................ 51 2.7.9 Effective Address Calculation ............................................................................. 53 2.8 Processing States............................................................................................................... 55 2.9 Usage Note........................................................................................................................ 56 2.9.1 Usage Notes on Bit-wise Operation Instructions ................................................. 56 Section 3 MCU Operating Modes 3.1 Operating Mode Selection ................................................................................................ 57 3.2 ...

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Section 5 Interrupt Controller 5.1 Features ............................................................................................................................. 85 5.2 Input/Output Pins .............................................................................................................. 87 5.3 Register Descriptions ........................................................................................................ 87 5.3.1 Interrupt Control Register (INTCR)..................................................................... 88 5.3.2 Interrupt Priority Registers (IPRA to IPRK) ............................................ 88 5.3.3 IRQ Enable Register ...

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Bus Control Register (BCR) ................................................................................ 136 6.3.8 DRAM Control Register (DRAMCR) ................................................................. 138 6.3.9 DRAM Access Control Register (DRACCR) ...................................................... 144 6.3.10 Refresh Control Register (REFCR) ..................................................................... 149 6.3.11 Refresh Timer Counter (RTCNT)........................................................................ 152 6.3.12 Refresh Time Constant Register ...

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Precharge State Count.......................................................................................... 208 6.7.10 Bus Cycle Control in Write Cycle ....................................................................... 210 6.7.11 Byte Access Control ............................................................................................ 211 6.7.12 Burst Operation.................................................................................................... 214 6.7.13 Refresh Control.................................................................................................... 217 6.7.14 Mode Register Setting of Synchronous DRAM................................................... 223 6.7.15 DMAC and EXDMAC ...

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DMA Terminal Control Register (DMATCR)..................................................... 285 7.4 Activation Sources ............................................................................................................ 286 7.4.1 Activation by Internal Interrupt Request.............................................................. 287 7.4.2 Activation by External Request ........................................................................... 287 7.4.3 Activation by Auto-Request................................................................................. 288 7.5 Operation .......................................................................................................................... 288 7.5.1 Transfer Modes .................................................................................................... 288 ...

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EXDMA Mode Control Register (EDMDR) ....................................................... 341 8.3.5 EXDMA Address Control Register (EDACR) .................................................... 346 8.4 Operation .......................................................................................................................... 350 8.4.1 Transfer Modes .................................................................................................... 350 8.4.2 Address Modes .................................................................................................... 351 8.4.3 DMA Transfer Requests ...................................................................................... 355 8.4.4 Bus Modes ........................................................................................................... ...

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Block Transfer Mode ........................................................................................... 414 9.5.4 Chain Transfer ..................................................................................................... 415 9.5.5 Interrupt Sources.................................................................................................. 416 9.5.6 Operation Timing................................................................................................. 417 9.5.7 Number of DTC Execution States........................................................................ 418 9.6 Procedures for Using DTC................................................................................................ 420 9.6.1 Activation by Interrupt......................................................................................... 420 9.6.2 Activation by ...

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Port 5 Data Register (P5DR)................................................................................ 463 10.5.3 Port 5 Register (PORT5)...................................................................................... 464 10.5.4 Pin Functions ....................................................................................................... 464 10.6 Port 6................................................................................................................................. 467 10.6.1 Port 6 Data Direction Register (P6DDR)............................................................. 467 10.6.2 Port 6 Data Register (P6DR)................................................................................ 468 10.6.3 Port 6 ...

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Port D................................................................................................................................ 496 10.12.1 Port D Data Direction Register (PDDDR) ........................................................... 497 10.12.2 Port D Data Register (PDDR) .............................................................................. 497 10.12.3 Port D Register (PORTD) .................................................................................... 498 10.12.4 Port D Pull-up Control Register (PDPCR)........................................................... 498 10.12.5 Pin Functions ....................................................................................................... ...

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Timer General Register (TGR) ............................................................................ 557 11.3.8 Timer Start Register (TSTR)................................................................................ 557 11.3.9 Timer Synchronous Register (TSYR) .................................................................. 558 11.4 Operation .......................................................................................................................... 559 11.4.1 Basic Functions.................................................................................................... 559 11.4.2 Synchronous Operation........................................................................................ 564 11.4.3 Buffer Operation .................................................................................................. 566 11.4.4 Cascaded Operation ...

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PPG Output Mode Register (PMR)...................................................................... 613 12.4 Operation .......................................................................................................................... 615 12.4.1 Output Timing...................................................................................................... 616 12.4.2 Sample Setup Procedure for Normal Pulse Output.............................................. 617 12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output).......... 618 12.4.4 Non-Overlapping Pulse Output............................................................................ ...

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Contention between TCNT Write and Increment ................................................ 644 13.8.3 Contention between TCOR Write and Compare Match ...................................... 645 13.8.4 Contention between Compare Matches A and B ................................................. 646 13.8.5 Switching of Internal Clocks and TCNT Operation............................................. 646 13.8.6 Mode ...

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Operation in Asynchronous Mode .................................................................................... 691 15.4.1 Data Transfer Format........................................................................................... 691 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 693 15.4.3 Clock.................................................................................................................... 694 15.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 695 15.4.5 Data Transmission (Asynchronous Mode)........................................................... 696 ...

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Section 16 A/D Converter 16.1 Features ............................................................................................................................. 741 16.2 Input/Output Pins .............................................................................................................. 743 16.3 Register Descriptions ........................................................................................................ 744 16.3.1 A/D Data Registers (ADDRA to ADDRH).............................................. 744 16.3.2 A/D Control/Status Register (ADCSR) ............................................................... 746 16.3.3 A/D Control Register ...

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Flash Memory Control Register 1 (FLMCR1)..................................................... 781 19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 783 19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 784 19.5.4 Erase Block Register 2 (EBR2) ........................................................................... 785 19.5.5 RAM Emulation Register (RAMER)................................................................... 786 19.6 On-Board ...

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Module Stop Control Registers H and L (MSTPCRH, MSTPCRL).................... 824 22.2 Operation .......................................................................................................................... 825 22.2.1 Clock Division Mode........................................................................................... 825 22.2.2 Sleep Mode .......................................................................................................... 826 22.2.3 Software Standby Mode....................................................................................... 826 22.2.4 Hardware Standby Mode ..................................................................................... 829 22.2.5 Module Stop Mode ...

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Section 1 Overview Figure 1.1 H8S/2678 Group Internal Block Diagram ........................................................... Figure 1.2 H8S/2678R Group Internal Block Diagram......................................................... Figure 1.3 H8S/2678 Group Pin Arrangement...................................................................... Figure 1.4 H8S/2678R Group Pin Arrangement ................................................................... Section 2 CPU Figure 2.1 Exception Vector Table (Normal ...

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Figure 4.4 Operation when SP Value Is Odd ........................................................................ 83 Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller ................................................................ 86 Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 ...................................................... 102 Figure 5.3 Flowchart of Procedure Up ...

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Example of Access Timing when RAS Signal Goes Low from Beginning Figure 6. State (CAST = 0) ......................................................................................... 178 r Figure 6.24 Example of Timing with One Row Address Output Maintenance State (RAST = 0, CAST = 0) ...

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Figure 6.53 Example of Operation Timing in RAS Down Mode ( CAS Latency 2) .. 217 Figure 6.54 Auto Refresh Timing ........................................................................................... 218 Figure 6.55 Auto Refresh Timing (TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 ...

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Figure 6.80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2) .................. 245 Figure 6.81 Example of Timing for Idle Cycle Insertion in Case of ...

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Figure 7.29 Example of Single Address Mode Transfer (Word Write) .................................. 321 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer 322 Figure 7.30 Example of DREQ Pin Low Level Activated Single Address Mode Transfer .... 323 Figure ...

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Figure 8.23 Example of Single Address Mode (Word Read) Transfer ................................... 376 Figure 8.24 Example of Single Address Mode (Byte Write) Transfer.................................... 377 Figure 8.25 Example of Single Address Mode (Word Write) Transfer .................................. 377 Example of Single Address Mode ...

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Figure 8.45 Transfer End Interrupt Logic ............................................................................... 395 Figure 8.46 Example of Procedure for Restarting Transfer on Channel in which Transfer End Interrupt Occurred ........................................................................................ 397 Section 9 Data Transfer Controller (DTC) Figure 9.1 Block Diagram of DTC........................................................................................ 402 Figure ...

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Figure 11.22 Example of PWM Mode Operation (2)................................................................ 575 Figure 11.23 Example of PWM Mode Operation (3)................................................................ 576 Figure 11.24 Example of Phase Counting Mode Setting Procedure ......................................... 577 Figure 11.25 Example of Phase Counting Mode 1 Operation................................................... 578 Figure ...

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Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example) ......................... 621 Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary) ............ 622 Figure 12.10 Inverted Pulse Output (Example)......................................................................... 624 Figure 12.11 Pulse Output Triggered by Input Capture (Example) .......................................... 625 Section ...

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Figure 15.9 Sample Serial Reception Data Flowchart (2)....................................................... 701 Figure 15.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)......................................... 703 Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart....................................... 704 Figure 15.12 Example of SCI Operation ...

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Figure 16.3 External Trigger Input Timing............................................................................. 756 Figure 16.4 A/D Conversion Accuracy Definitions ................................................................ 758 Figure 16.5 A/D Conversion Accuracy Definitions ................................................................ 758 Figure 16.6 Example of Analog Input Circuit......................................................................... 759 Figure 16.7 Example of Analog Input Protection Circuit ....................................................... ...

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Section 22 Power-Down Modes Figure 22.1 Mode Transitions ................................................................................................. 821 Figure 22.2 Software Standby Mode Application Example.................................................... 829 Figure 22.3 Hardware Standby Mode Timing......................................................................... 830 Section 24 Electrical Characteristics Figure 24.1 Output Load Circuit ............................................................................................. 870 Figure 24.2 System Clock ...

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Figure 24.35 PPG Output Timing ............................................................................................. 903 Figure 24.36 TPU Input/Output Timing.................................................................................... 903 Figure 24.37 TPU Clock Input Timing ..................................................................................... 904 Figure 24.38 8-Bit Timer Output Timing.................................................................................. 904 Figure 24.39 8-Bit Timer Clock Input Timing.......................................................................... 904 Figure 24.40 8-Bit Timer ...

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Section 1 Overview Table 1.1 Pin Arrangement in Each Operating Mode ............................................................ Table 1.2 Pin Functions.......................................................................................................... 13 Section 2 CPU Table 2.1 Instruction Classification........................................................................................ 37 Table 2.2 Operation Notation................................................................................................. 38 Table 2.3 Data Transfer Instructions ...................................................................................... 39 Table 2.4 Arithmetic ...

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Section 6 Bus Controller (BSC) Table 6.1 Pin Configuration ................................................................................................... 123 Table 6.2 Bus Specifications for Each Area (Basic Bus Interface) ........................................ 155 Table 6.3 Data Buses Used and Valid Strobes ....................................................................... 160 Table 6.4 Relation between Settings of Bits ...

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Table 9.4 Register Function in Repeat Mode ......................................................................... 413 Table 9.5 Register Function in Block Transfer Mode ............................................................ 414 Table 9.6 DTC Execution Status ............................................................................................ 418 Table 9.7 Number of States Required for Each Execution Status .......................................... 419 Section 10 ...

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Table 11.28 Register Combinations in Buffer Operation........................................................... 567 Table 11.29 Cascaded Combinations ......................................................................................... 570 Table 11.30 PWM Output Registers and Output Pins................................................................ 573 Table 11.31 Clock Input Pins in Phase Counting Mode............................................................. 577 Table 11.32 Up/Down-Count Conditions in Phase Counting ...

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Table 15.12 Settings of Bits IrCKS2 to IrCKS0 ........................................................................ 732 Table 15.13 SCI Interrupt Sources ............................................................................................. 734 Table 15.14 SCI Interrupt Sources ............................................................................................. 734 Section 16 A/D Converter Table 16.1 A/D Converter Pins ................................................................................................ 743 Table 16.2 Analog Input Channels ...

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Table 24.4 Permissible Output Currents .................................................................................. 869 Table 24.5 Clock Timing ......................................................................................................... 871 Table 24.6 Control Signal Timing............................................................................................ 874 Table 24.7 Bus Timing............................................................................................................. 876 Table 24.8 Bus Timing............................................................................................................. 877 Table 24.9 DMAC and EXDMAC Timing .............................................................................. 898 Table 24.10 Timing ...

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Rev. 3.00 Mar 17, 2006 page ...

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Features High-speed H8S/2600 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 69 basic instructions Various peripheral functions DMA controller (DMAC) EXDMA controller (EXDMAC) Data transfer ...

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Section 1 Overview Compact package Product Package H8S/2678 Group QFP-144 H8S/2678R Group LQFP-144 FP-144H Rev. 3.00 Mar 17, 2006 page 2 of 926 REJ09B0283-0300 (Code) Mounting Height Body Size FP-144G 3.05 mm (Max.) 1.70 mm (Max.) Pin Pitch 22.0 22.0 ...

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Block Diagram MD2 MD1 MD0 EXTAL XTAL STBY RES WDTOVF FWE * 2 NMI PF7/ PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/LCAS/IRQ15 PF1/UCAS/IRQ14 PF0/WAIT PG6/BREQ PG5/BACK PG4/BREQO PG3/CS3 PG2/CS2 PG1/CS1 PG0/CS0 P65/TMO1/DACK1/IRQ13 P64/TMO0/DACK0/IRQ12 P63/TMCI1/TEND1/IRQ11 P62/TMCI0/TEND0/IRQ10 P61/TMRI1/DREQ1/IRQ9 P60/TMRI0/DREQ0/IRQ8 P85/EDACK3/(IRQ5) P84/EDACK2/(IRQ4) P83/ETEND3/(IRQ3) P82/ETEND2/(IRQ2) ...

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Section 1 Overview MD2 MD1 MD0 DCTL EXTAL XTAL STBY RES WDTOVF NMI PF7/ PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/LCAS/IRQ15/DQML PF1/UCAS/IRQ14/DQMU PF0/WAIT PG6/BREQ PG5/BACK PG4/BREQO PG3/CS3/RAS3/CAS PG2/CS2/RAS2/RAS PG1/CS1 PG0/CS0 P65/TMO1/DACK1/IRQ13 P64/TMO0/DACK0/IRQ12 P63/TMCI1/TEND1/IRQ11 P62/TMCI0/TEND0/IRQ10 P61/TMRI1/DREQ1/IRQ9 P60/TMRI0/DREQ0/IRQ8 P85/EDACK3/(IRQ5) P84/EDACK2/(IRQ4) P83/ETEND3/(IRQ3) P82/ETEND2/(IRQ2) P81/EDREQ3/(IRQ1) P80/EDREQ2/(IRQ0) ...

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Pin Description 1.3.1 Pin Arrangement P52/SCK2/IRQ2 109 P53/ADTRG/IRQ3 110 PH2/CS6/(IRQ6) 111 PH3/CS7/OE/(IRQ7) 112 PG4/BREQO 113 PG5/BACK 114 PG6/BREQ 115 Vcc 116 P40/AN0 117 P41/AN1 118 P42/AN2 119 P43/AN3 120 Vref 121 AVcc 122 P44/AN4 123 P45/AN5 124 P46/AN6/DA0 125 ...

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Section 1 Overview P52/SCK2/IRQ2 109 P53/ADTRG/IRQ3 110 PH2/CS6/(IRQ6) 111 PH3/CS7/OE/(IRQ7) 112 PG4 / BREQO 113 PG5 /BACK 114 PG6 /BREQ 115 116 P40 / AN0 117 P41 / AN1 118 P42 / AN2 119 P43 / AN3 ...

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Pin Arrangement in Each Operating Mode Table 1.1 Pin Arrangement in Each Operating Mode Pin No. Modes 1 and 5 Modes 2 and 6 1 MD2 MD2 2 P83/ETEND3/ P83/ETEND3/ (IRQ3) (IRQ3) 3 P84/EDACK2/ P84/EDACK2/ (IRQ4) (IRQ4) 4 P85/EDACK3/ ...

Page 60

Section 1 Overview Pin No. Modes 1 and 5 Modes 2 and 6 27 A18 A18 28 A19 A19 29 A20 A20 30 PA5/A21 PA5/A21 31 PA6/A22 PA6/A22 32 PA7/A23 PA7/A23 P70/EDREQ0/ P70/EDREQ0/ (DREQ0) (DREQ0) 35 ...

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Pin No. Modes 1 and 5 Modes 2 and 6 51 P17/PO15/ P17/PO15/ TIOCB2/TCLKD/ TIOCB2/TCLKD/ EDRAK3 EDRAK3 52 P20/PO0/ P20/PO0/ TIOCA3/(IRQ8) TIOCA3/(IRQ8) 53 P21/PO1/ P21/PO1/ TIOCB3/(IRQ9) TIOCB3/(IRQ9) 54 P22/PO2/ P22/PO2/ TIOCC3/(IRQ10) TIOCC3/(IRQ10) 55 P23/PO3/ P23/PO3/ TIOCD3/(IRQ11) TIOCD3/(IRQ11) 56 P24/PO4/ P24/PO4/ ...

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Section 1 Overview Pin No. Modes 1 and 5 Modes 2 and 6 73 D14 D14 74 D13 D13 75 D12 D12 76 Vss Vss 77 D11 D11 78 D10 D10 P62/TMCI0/ P62/TMCI0/ ...

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Pin No. Modes 1 and 5 Modes 2 and 6 101 PG0/CS0 PG0/CS0 102 PG1/CS1 PG1/CS1 103 PG2/CS2/ PG2/CS2/ RAS2 * RAS2 * /RAS * /RAS * 104 PG3/CS3/ PG3/CS3/ RAS3 * RAS3 * /CAS * /CAS ...

Page 64

Section 1 Overview Pin No. Modes 1 and 5 Modes 2 and 6 128 P55/AN13/IRQ5 P55/AN13/IRQ5 129 P56/AN14/DA2/ P56/AN14/DA2/ IRQ6 IRQ6 130 P57/AN15/DA3/ P57/AN15/DA3/ IRQ7 IRQ7 131 AVss AVss 132 DCTL * DCTL * ...

Page 65

Pin Functions Table 1.2 Pin Functions FP-144G (H8S/2678 Type Symbol Group) Power supply V 5, 39, 67, CC 96, 116 V 12, 19, 26, SS 47, 76, 99, 136 PLLV 94 CC PLLV 92 SS Clock XTAL 98 EXTAL ...

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Section 1 Overview FP-144G (H8S/2678 Type Symbol Group) Operating DCTL — mode control RES System 93 control STBY 100 BREQ 115 BREQO 113 BACK 114 FWE 62 Address bus A23 27 20 ...

Page 67

FP-144G (H8S/2678 Type Symbol Group) RD Bus control 90 HWR 89 LWR 88 UCAS 86 LCAS 87 DQMU — DQML — RAS/ — RAS2 RAS3 to RAS5 RAS — Pin No. FP-144H (H8S/2678R I/O Function Group) 90 Output When this ...

Page 68

Section 1 Overview FP-144G (H8S/2678 Type Symbol Group) CAS Bus control — WE — WAIT 85 OE 112, 133 (OE) CKE — (CKE) Interrupt NMI 38 signals IRQ15 to 87, 86, IRQ0 84 to 81, 61, 60, 130 to 127, ...

Page 69

FP-144G (H8S/2678 Type Symbol Group) TEND1 DMA controller 82, 81, TEND0 (DMAC) 40, 36 (TEND1) (TEND0) DACK1 84, 83, DACK0 42, 41 (DACK1) (DACK0) EDREQ3 EXDMA 141, 140, controller to 35, 34 EDREQ0 (EXDMAC) ETEND3 2, 142, to 40, 36 ...

Page 70

Section 1 Overview FP-144G (H8S/2678 Type Symbol Group) 16-bit timer TIOCA2 50, 51 pulse unit TIOCB2 (TPU) TIOCA3 52, 53, TIOCB3 54, 55 TIOCC3 TIOCD3 TIOCA4 56, 57 TIOCB4 TIOCA5, 58, 59 TIOCB5 Programmable PO15 48, pulse ...

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FP-144G (H8S/2678 Type Symbol Group) A/D converter AN15 to 130 to 127, AN12, 126 to 123, AN7 to 120 to 117 AN0 ADTRG 110 D/A converter DA3 to 130, 129, DA0 126, 125 A/D converter, AV 122 CC D/A converter ...

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Section 1 Overview FP-144G (H8S/2678 Type Symbol Group) I/O ports P57 to 130 to 127 130 to 127 P54 P53 to 110 to 107 110 to 107 P50 P65 81, P60 61, 60 P75 ...

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The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...

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Section 2 CPU 16 16-bit register-register multiply: 4 states 32 ÷ 16-bit register-register divide: 20 states Two CPU operating modes Normal mode * Advanced mode Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection Note: * ...

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More general registers and control registers Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a ...

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Section 2 CPU 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the ...

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H'0000 Reset exception vector H'0001 H'0002 (Reserved for system use) H'0003 H'0004 H'0005 (Reserved for system use) H'0006 H'0007 H'0008 Exception vector 1 H'0009 H'000A Exception vector 2 H'000B Figure 2.1 Exception Vector Table (Normal Mode (16 bits) ...

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Section 2 CPU 2.2.2 Advanced Mode Address Space Linear access is provided to a 16-Mbyte maximum address space. Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers the upper 16-bit segments of ...

Page 79

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a ...

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Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in ...

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Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended register (EXR), an 8-bit condition ...

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Section 2 CPU 2.4.1 General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a ...

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SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When ...

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Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the ...

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Bit Bit Name Initial Value 2 Z Undefined 1 V Undefined 0 C Undefined 2.4.5 Multiply-Accumulate Register (MAC) This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32- bit registers denoted MACH and MACL. The lower ...

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Section 2 CPU 2.5 Data Formats The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … ...

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Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn : General register General register General register R RnH : General register RH RnL ...

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Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, but word or longword data must begin at an even address ...

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Instruction Set The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV POP * , PUSH * 1 LDM, STM MOVFPE * Arithmetic ...

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Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register ...

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Table 2.3 Data Transfer Instructions Size * Instruction Function MOV B/W/L (EAs) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this ...

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Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Size * Instruction Function ADD B/W/L Rd ± Rs SUB Performs addition or subtraction on data in two general registers immediate data and data in a general register. (Immediate ...

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Table 2.4 Arithmetic Operations Instructions (2) Size * 1 Instruction Function DIVXS B/W Rd ÷ Rs Performs signed division on data in two general registers: either 16 bits ÷ 8 bits 32 bits ÷ 16 bits CMP B/W/L Rd – ...

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Section 2 CPU Table 2.5 Logic Operations Instructions Size * Instruction Function AND B/W/L Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Performs a logical OR operation on ...

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Table 2.7 Bit Manipulation Instructions (1) Size * Instruction Function BSET B 1 Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits ...

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Section 2 CPU Table 2.7 Bit Manipulation Instructions (2) Size * Instruction Function BXOR B C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR ...

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Table 2.8 Branch Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC ...

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Section 2 CPU Table 2.9 System Control Instructions Size * Instruction Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) Moves the contents ...

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Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L else next; EEPMOV.W — else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set ...

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Section 2 CPU (1) Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension op (4) Operation field, effective address extension, and condition field op Figure 2.11 Instruction Formats (Examples) 2.7 ...

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Table 2.11 Addressing Modes No. Addressing Mode 1 Register direct 2 Register indirect 3 Register indirect with displacement 4 Register indirect with post-increment Register indirect with pre-decrement 5 Absolute address 6 Immediate 7 Program-counter relative 8 Memory indirect 2.7.1 Register ...

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Section 2 CPU 2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn Register indirect with post-increment—@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is ...

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Immediate—#xx:8, #xx:16, or #xx:32 The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data ...

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Section 2 CPU Specified Branch address by @aa:8 (a) Normal Mode Note: * Normal mode is not available in this LSI. Figure 2.12 Branch Address Specification in Memory Indirect Mode Rev. 3.00 Mar 17, 2006 page 52 of 926 REJ09B0283-0300 ...

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Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is ...

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Section 2 CPU Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate Note: * Normal mode is not available in this LSI. Rev. 3.00 Mar 17, 2006 page 54 of 926 REJ09B0283-0300 Effective Address Calculation ...

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Processing States The H8S/2600 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. Reset State The CPU and on-chip peripheral modules ...

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Section 2 CPU Bus-released state Exception handling state RES = High Reset state * 1 Reset state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can ...

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Section 3 MCU Operating Modes 3.1 Operating Mode Selection The H8S/2678 Group has twelve operating modes (modes and 10 to 15). All operating modes are available for the flash memory version. Modes 1, 2, and ...

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Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection MCU Operating Mode * FWE * 1 2 MD2 MD1 MD0 — ...

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Mode Control Register (MDCR) MDCR monitors the current operating mode of the H8S/2678 Group chip. Bit Bit Name Initial Value 7 to — All MDS2 —* 1 MDS1 —* 0 MDS0 —* Note: * Determined by ...

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Section 3 MCU Operating Modes Bit Bit Name Initial Value 3 FLSHE 0 2 — EXPE — 0 RAME 1 Note: * Mode 3 is available only in the F-ZTAT version of H8S/2678R Group. Rev. 3.00 Mar 17, ...

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Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports function as an address bus, ports D and E function as a data ...

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Section 3 MCU Operating Modes 3.3.5 Mode 5 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. The program in an external ROM connected to the first half of area 0 is executed. ...

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Mode 10 This is flash memory boot mode. This mode is the same as mode 4, except for accessing to the flash memory. Mode 10 is available only in the flash memory version of the H8S/2678 Group. 3.3.9 Mode ...

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Section 3 MCU Operating Modes Table 3.2 Pin Functions in Each Operating Mode Mode Mode Mode Port Port A PA7 PA5 PA4 PA0 Port Port ...

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Memory Map in Each Operating Mode Figures 3.1 to 3.6 show memory maps for each product. RAM: 8 kbytes Modes 1 and 2 (expanded modes with on-chip ROM disabled) H'000000 address space H'FFA000 On-chip RAM/external address space* H'FFC000 External ...

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Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 8 kbytes Modes 5 and 6 (external ROM activation expanded modes with on-chip ROM enabled) H'000000 address space H'100000 On-chip ROM H'140000 address space H'FFA000 On-chip RAM/external address space * H'FFC000 ...

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ROM: 256 kbytes RAM: 8 kbytes Mode 10 Boot mode (expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'040000 External address space H'FFA000 On-chip RAM * H'FFC000 External address space H'FFFC00 Internal I/O registers H'FFFF00 External address space H'FFFF20 ...

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Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 8 kbytes Mode 12 User program mode (expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'040000 External address space H'FFA000 On-chip RAM * 2 H'FFC000 External address space H'FFFC00 Internal ...

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RAM: 8 kbytes Modes 1 and 2 (expanded modes with on-chip ROM disabled) H'000000 External address space H'FFA000 On-chip RAM/external address space * H'FFC000 External address space H'FFFC00 Internal I/O registers H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF ...

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Section 3 MCU Operating Modes ROM: 128 kbytes RAM: 8 kbytes Modes 5 and 6 (external ROM activation expanded modes with on-chip ROM enabled) H'000000 address space H'100000 On-chip ROM H'120000 address space H'FFA000 On-chip RAM/external address space * H'FFC000 ...

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RAM: 8 kbytes Modes 1 and 2 (expanded modes with on-chip ROM disabled) H'000000 External address space H'FFA000 On-chip RAM/external address space * H'FFC000 External address space H'FFFC00 Internal I/O registers H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF ...

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Section 3 MCU Operating Modes ROM: 64 kbytes RAM: 8 kbytes Modes 5 and 6 (external ROM activation expanded modes with on-chip ROM enabled) H'000000 address space H'100000 On-chip ROM H'110000 address space H'FFA000 On-chip RAM/external address space * H'FFC000 ...

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H'000000 H'FFA000 H'FFC000 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF Note: * This area is specified as an external address area by clearing the RAME bit of SYSCR to 0. Figure 3.4 H8S/2670 Memory Map Section 3 MCU Operating Modes RAM: 8 kbytes ...

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Section 3 MCU Operating Modes Note: * This area is specified as an external address area by clearing the RAME bit of SYSCR to 0. Figure 3.5 H8S/2674R Memory Map Rev. 3.00 Mar 17, 2006 page 74 of 926 REJ09B0283-0300 ...

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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more ...

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Section 4 Exception Handling Table 4.2 Exception Handling Vector Table Exception Source Power-on reset Manual reset * 2 Reserved for system use Trace Interrupt (direct transition Interrupt (NMI) Trap instruction (#0) (#1) (#2) (#3) Reserved for system use ...

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Exception Source External interrupt IRQ13 IRQ14 IRQ15 Internal interrupt * 3 Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI. 3. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling Vector Table. ...

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Section 4 Exception Handling RES Internal address bus Internal read signal Internal write signal Internal data bus (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ...

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RES Address bus RD HWR, LWR D15 to D0 (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * ...

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Section 4 Exception Handling Consequently, on-chip peripheral module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited. 4.4 Traces Traces are enabled in interrupt control mode 2. Trace mode is ...

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The interrupt exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack. 2. The interrupt mask bit is updated and the T bit is ...

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Section 4 Exception Handling 4.7 Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes (b) Advanced Modes Notes: 1. Ignored on return. 2. Normal modes ...

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Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack ...

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Section 4 Exception Handling Rev. 3.00 Mar 17, 2006 page 84 of 926 REJ09B0283-0300 ...

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Section 5 Interrupt Controller 5.1 Features Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). Priorities settable with IPR An interrupt priority ...

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Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 INTCR NMIEG NMI input NMI input unit IRQ input unit IRQ input ISR ITSR SSIER Internal interrupt sources SWDTEND to TEI Interrupt ...

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Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O NMI Input IRQ15 to IRQ0 Input 5.3 Register Descriptions The interrupt controller has the following registers. Interrupt control register (INTCR) IRQ ...

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Section 5 Interrupt Controller 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Bit Name Initial Value 7, 6 — All 0 5 INTM1 0 4 INTM0 0 3 NMIEG 0 ...

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Bit Bit Name Initial Value 15 — IPR14 1 13 IPR13 1 12 IPR12 1 11 — IPR10 1 9 IPR9 1 8 IPR8 1 7 — 0 Section 5 Interrupt Controller R/W Description — Reserved ...

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Section 5 Interrupt Controller Bit Bit Name Initial Value 6 IPR6 1 5 IPR5 1 4 IPR4 1 3 — IPR2 1 1 IPR1 1 0 IPR0 1 Rev. 3.00 Mar 17, 2006 page 90 of 926 REJ09B0283-0300 ...

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IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ15 to IRQ0. Bit Bit Name Initial Value 15 IRQ15E 0 14 IRQ14E 0 13 IRQ13E 0 12 IRQ12E 0 11 IRQ11E 0 10 IRQ10E 0 9 ...

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Section 5 Interrupt Controller Bit Bit Name Initial Value 5 IRQ5E 0 4 IRQ4E 0 3 IRQ3E 0 2 IRQ2E 0 1 IRQ1E 0 0 IRQ0E 0 5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCR select the ...

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Bit Bit Name Initial Value 13 IRQ14SCB 0 12 IRQ14SCA 0 11 IRQ13SCB 0 10 IRQ13SCA 0 9 IRQ12SCB 0 8 IRQ12SCA 0 Section 5 Interrupt Controller R/W Description R/W IRQ14 Sense Control B R/W IRQ14 Sense Control A 00: ...

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Section 5 Interrupt Controller Bit Bit Name Initial Value 7 IRQ11SCB 0 6 IRQ11SCA 0 5 IRQ10SCB 0 4 IRQ10SCA 0 3 IRQ9SCB 0 2 IRQ9SCA 0 Rev. 3.00 Mar 17, 2006 page 94 of 926 REJ09B0283-0300 R/W Description R/W ...

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Bit Bit Name Initial Value 1 IRQ8SCB 0 0 IRQ8SCA 0 ISCRL Bit Bit Name Initial Value 15 IRQ7SCB 0 14 IRQ7SCA 0 13 IRQ6SCB 0 12 IRQ6SCA 0 Section 5 Interrupt Controller R/W Description R/W IRQ8 Sense Control B ...

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Section 5 Interrupt Controller Bit Bit Name Initial Value 11 IRQ5SCB 0 10 IRQ5SCA 0 9 IRQ4SCB 0 8 IRQ4SCA 0 7 IRQ3SCB 0 6 IRQ3SCA 0 Rev. 3.00 Mar 17, 2006 page 96 of 926 REJ09B0283-0300 R/W Description R/W ...

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Bit Bit Name Initial Value 5 IRQ2SCB 0 4 IRQ2SCA 0 3 IRQ1SCB 0 2 IRQ1SCA 0 1 IRQ0SCB 0 0 IRQ0SCA 0 Section 5 Interrupt Controller R/W Description R/W IRQ2 Sense Control B R/W IRQ2 Sense Control A 00: ...

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Section 5 Interrupt Controller 5.3.5 IRQ Status Register (ISR) ISR is an IRQ15 to IRQ0 interrupt request flag register. Bit Bit Name Initial Value 15 IRQ15F 0 14 IRQ14F 0 13 IRQ13F 0 12 IRQ12F 0 11 IRQ11F 0 10 ...

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Bit Bit Name Initial Value 13 ITS13 0 12 ITS12 0 11 ITS11 0 10 ITS10 0 9 ITS9 0 8 ITS8 0 7 ITS7 0 6 ITS6 0 5 ITS5 0 4 ITS4 0 Section 5 Interrupt Controller R/W ...

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Section 5 Interrupt Controller Bit Bit Name Initial Value 3 ITS3 0 2 ITS2 0 1 ITS1 0 0 ITS0 0 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects the IRQ pins used to recover from the software ...

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Interrupt Sources 5.4.1 External Interrupts There are seventeen external interrupts: NMI and IRQ15 to IRQ0. These interrupts can be used to restore the chip from software standby mode. NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and ...

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Section 5 Interrupt Controller IRQnSCA, IRQnSCB Edge/ level detection circuit IRQn input Note Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 5.4.2 Internal Interrupts The sources for internal interrupts from on-chip peripheral modules have ...

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Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Interrupt Vector Source Source Number External NMI 7 pin IRQ0 16 IRQ1 17 IRQ2 18 IRQ3 19 IRQ4 20 IRQ5 21 IRQ6 22 IRQ7 23 IRQ8 24 IRQ9 ...

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Section 5 Interrupt Controller Origin of Interrupt Interrupt Vector Source Source Number TPU_0 TGI0A 40 TGI0B 41 TGI0C 42 TGI0D 43 TCI0V 44 — Reserved for 45 system use 46 47 TPU_1 TGI1A 48 TGI1B 49 TCI1V 50 TCI1U 51 ...

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Origin of Interrupt Interrupt Vector Source Source Number TPU_5 TGI5A 68 TGI5B 69 TCI5V 70 TCI5U 71 TMR_0 CMIA0 72 CMIB0 73 OVI0 74 — Reserved for 75 system use TMR_1 CMIA1 76 CMIB1 77 OVI1 78 — Reserved for ...

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Section 5 Interrupt Controller Origin of Interrupt Interrupt Vector Source Source Number SCI_2 ERI2 96 RXI2 97 TXI2 98 TEI2 99 — Reserved for 100 system use 101 102 103 — Reserved for 104 system use 105 106 107 108 ...

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Origin of Interrupt Interrupt Vector Source Source Number — Reserved for 120 system use 121 122 123 124 125 126 127 Note: * Lower 16 bits of the start address. 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller ...

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Section 5 Interrupt Controller 5.6.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests except for NMI is masked by the I bit of CCR in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation ...

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Program execution status Interrupt generated? Yes IRQ0 Yes Save PC and CCR Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Section 5 Interrupt Controller No Yes ...

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Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level ( bits) in the ...

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Program execution status Interrupt generated? Yes No Level 7 interrupt? Yes Level 6 interrupt? No Mask level 6 or below? Yes Mask level 5 or below? Save PC, CCR, and EXR Clear T bit to 0 Update mask level Read ...

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Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack ...

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Figure 5.5 Interrupt Exception Handling Section 5 Interrupt Controller Rev. 3.00 Mar 17, 2006 page 113 of 926 REJ09B0283-0300 ...

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Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in ...

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Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Symbol Instruction fetch S I Branch address read S J Stack manipulation S K Legend: m: Number of wait states in an external device access 5.6.5 DTC and DMAC ...

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Section 5 Interrupt Controller Interrupt request IRQ interrupt Interrupt source On-chip clear signal supporting module Interrupt controller Figure 5.6 DTC, DMAC, and Interrupt Controller (1) Selection of Interrupt Source: The activation factors for each channel of DMAC are selected by ...

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Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. If the same interrupt is selected as the ...

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Section 5 Interrupt Controller priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.7 ...

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Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With ...

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Section 5 Interrupt Controller Rev. 3.00 Mar 17, 2006 page 120 of 926 REJ09B0283-0300 ...

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Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus ...

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Section 6 Bus Controller (BSC) A block diagram of the bus controller is shown in figure 6.1. EXDMAC address bus Internal address bus Internal bus master bus request signal EXDMAC bus request signal Internal bus master bus acknowledge signal EXDMAC ...

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Input/Output Pins Table 6.1 shows the pin configuration of the bus controller. Table 6.1 Pin Configuration Name Symbol AS Address strobe RD Read HWR High write/write enable LWR Low write CS0 Chip select 0 CS1 Chip select 1 CS2/ ...

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Section 6 Bus Controller (BSC) Name Symbol CS5/ Chip select 5/row address RAS5/ * strobe 5/SDRAM * SDRAM * CS6 Chip select 6 CS7 Chip select 7 UCAS/ Upper column address DQMU * strobe/upper data mask enable LCAS/ Lower column ...

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Name Symbol EDACK1 Data transfer acknowledge 1 (EXDMAC) EDACK0 Data transfer acknowledge 0 (EXDMAC) Note: * These pins are not supported in the H8S/2678 Group. 6.3 Register Descriptions The bus controller has the following registers. Bus width control register (ABWCR) ...

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Section 6 Bus Controller (BSC) 6.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area in the external address space as either 8-bit access space or 16-bit access space. Initial Value * Bit Bit Name 7 ABW7 1/0 6 ABW6 ...

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Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL) WTCRA and WTCRB select the number of program wait states for each area in the external address space. In addition, CAS latency is set when a ...

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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value 10 W62 1 9 W61 1 8 W60 1 WTARAL Bit Bit Name Initial Value 7 — W52 1 5 W51 1 4 W50 1 3 — 0 ...

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Bit Bit Name Initial Value 2 W42 1 1 W41 1 0 W40 1 WTCRBH Bit Bit Name Initial Value 15 — W32 1 13 W31 1 12 W30 1 11 — 0 Section 6 Bus Controller (BSC) ...

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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value 10 W22 1 9 W21 1 8 W20 1 Note: * The synchronous DRAM interface is not supported in the H8S/2678 Group. Legend: x: Don’t care. Rev. 3.00 Mar 17, ...

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WTCRBL Bit Bit Name Initial Value 7 — W12 1 5 W11 1 4 W10 1 3 — W02 1 1 W01 1 0 W00 1 Section 6 Bus Controller (BSC) R/W Description R Reserved This ...

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Section 6 Bus Controller (BSC) 6.3.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access. Bit Bit Name Initial Value 7 RDN7 0 6 RDN6 0 5 ...

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CS Assertion Period Control Registers H, L (CSACRH, CSACRL 6.3.5 CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip select signals (CSn) and address signals extended. Extending ...

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Section 6 Bus Controller (BSC) Address CS RD Read Data HWR, LWR Write Data Figure 6 and Address Assertion Period Extension (Example of 3-State Access Space CS Rev. 3.00 Mar 17, 2006 page 134 of 926 REJ09B0283-0300 ...

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Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1 burst ROM interface settings can be made ...

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Section 6 Bus Controller (BSC) 6.3.7 Bus Control Register (BCR) BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT ...

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Bit Bit Name Initial Value 10 ICIS0 1 9 WDBE 0 8 WAITE 0 7 — ICIS2 — All 0 Section 6 Bus Controller (BSC) R/W Description R/W Idle Cycle Insert 0 When ...

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Section 6 Bus Controller (BSC) 6.3.8 DRAM Control Register (DRAMCR) DRAMCR is used to make DRAM/synchronous DRAM * interface settings. Note: * The synchronous DRAM interface is not supported in the H8S/2678 Group. Bit Bit Name Initial Value 15 OEE ...

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Bit Bit Name Initial Value 12 CAST 0 11 — RMTS2 0 9 RMTS1 0 8 RMTS0 0 Section 6 Bus Controller (BSC) R/W Description R/W Column Address Output Cycle Number Select Selects whether the column address output ...

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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value RCDM 0 Rev. 3.00 Mar 17, 2006 page 140 of 926 REJ09B0283-0300 R/W Description R/W Burst Access Enable Selects enabling or disabling of burst access to ...

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Bit Bit Name Initial Value 5 DDS 0 4 EDDS 0 3 — 0 Section 6 Bus Controller (BSC) R/W Description R/W DMAC Single Address Transfer Option Selects whether full access is always performed or burst access is enabled when ...

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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value 2 MXC2 0 1 MXC1 0 0 MXC0 0 Rev. 3.00 Mar 17, 2006 page 142 of 926 REJ09B0283-0300 R/W Description R/W Address Multiplex Select R/W These bits select the ...

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Bit Bit Name Initial Value Section 6 Bus Controller (BSC) R/W Description 011: 11-bit shift When 8-bit access space is designated: Row address bits A23 to A11 used for comparison When 16-bit access space is designated: Row address bits A23 ...

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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value Address RAST = 0 RAS RAST = 1 RAS UCAS, LCAS Figure 6.4 RAS (2-State Column Address Output Cycle, Full Access) 6.3.9 DRAM Access Control Register (DRACCR) DRACCR is used ...

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H8S/2678 Group Bit Bit Name Initial Value 7 DRMI 0 6 — TPC1 0 4 TPC0 — All 0 1 RCD1 0 0 RCD0 0 Section 6 Bus Controller (BSC) R/W Description R/W Idle Cycle ...

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Section 6 Bus Controller (BSC) H8S/2678R Group Bit Bit Name Initial Value 15 DRMI 0 14 — TPC1 0 12 TPC0 0 11 SDWCD 0 10 — 0 Rev. 3.00 Mar 17, 2006 page 146 of 926 REJ09B0283-0300 ...

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Bit Bit Name Initial Value 9 RCD1 0 8 RCD0 — All 0 3 CKSPE 0 2 — RDXC1 0 0 RDXC0 0 Section 6 Bus Controller (BSC) R/W Description R/W RAS-CAS Wait Control ...

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Section 6 Bus Controller (BSC) Address bus Precharge-sel RAS SDWCD 0 CAS WE CKE DQMU, DQML Data bus Address bus Precharge-sel RAS SDWCD 1 CAS WE CKE DQMU, DQML Data bus Figure 6.5 CAS Latency Control Cycle Disable Timing during ...

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