HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 226

IC H8S MCU FLASH 256K 144-QFP

HD64F2676VFC33

Manufacturer Part Number
HD64F2676VFC33
Description
IC H8S MCU FLASH 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2676VFC33

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Section 2 Instruction Descriptions
2.2.59 (1)
SHLL (SHift Logical Left)
Operation
Rd (left logical shift)
Assembly-Language Format
SHLL.B Rd
Operand Size
Byte
Description
This instruction shifts the bits in an 8-bit register Rd (destination operand) one bit to the left. The
most significant bit (bit 7) shifts into the carry flag. The least significant bit (bit 0) is cleared to 0.
Available Registers
Rd: R0L to R7L, R0H to R7H
Operand Format and Number of States Required for Execution
Notes
The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag.
Rev. 4.00 Feb 24, 2006 page 210 of 322
REJ09B0139-0400
Register direct
Addressing
Mode
SHLL (B)
Mnemonic
SHLL.B
C
Rd
MSB
Operands
b7
Rd
. . . . . .
1st byte
1
0
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Always cleared to 0.
C: Receives the previous value in bit 7.
2nd byte
0
Instruction Format
cleared to 0.
cleared to 0.
I
rd
UI H
3rd byte
LSB
b0
U
N
0
4th byte
Z
Shift Logical
V
0
States
No. of
C
1

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