HD64F2633F25 Renesas Electronics America, HD64F2633F25 Datasheet - Page 171

IC H8S MCU FLASH 256K 128QFP

HD64F2633F25

Manufacturer Part Number
HD64F2633F25
Description
IC H8S MCU FLASH 256K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of HD64F2633F25

Core Processor
H8S/2600
Core Size
16-Bit
Speed
25MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
73
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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2.2.44 (1)
NEG (NEGate)
Operation
0 – Rd
Assembly-Language Format
NEG.B Rd
Operand Size
Byte
Description
This instruction takes the two’s complement of the contents of an 8-bit register Rd (destination
operand) and stores the result in the 8-bit register Rd (subtracting the register contents from H'00).
If the original contents of Rd were H'80, however, the result remains H'80.
Available Registers
Rd: R0L to R7L, R0H to R7H
Operand Format and Number of States Required for Execution
Notes
An overflow occurs if the original contents of Rd were H'80.
Register direct
Addressing
Mode
Rd
NEG (B)
Mnemonic
NEG.B
Operands
Rd
1st byte
1
7
Condition Code
H: Set to 1 if there is a borrow at bit 3;
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Set to 1 if there is a borrow at bit 7;
2nd byte
8
Instruction Format
otherwise cleared to 0.
cleared to 0.
cleared to 0.
cleared to 0.
otherwise cleared to 0.
Rev. 4.00 Feb 24, 2006 page 155 of 322
I
rd
UI H
Section 2 Instruction Descriptions
3rd byte
U
Negate Binary Signed
N
4th byte
REJ09B0139-0400
Z
V
States
No. of
C
1

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