IC H8S MCU FLASH 128K 128QFP

HD64F2636F20J

Manufacturer Part NumberHD64F2636F20J
DescriptionIC H8S MCU FLASH 128K 128QFP
ManufacturerRenesas Electronics America
SeriesH8® H8S/2600
HD64F2636F20J datasheets
 


Specifications of HD64F2636F20J

Core ProcessorH8S/2600Core Size16-Bit
Speed20MHzConnectivityCAN, SCI, SmartCard
PeripheralsMotor Control PWM, POR, PWM, WDTNumber Of I /o72
Program Memory Size128KB (128K x 8)Program Memory TypeFLASH
Ram Size4K x 8Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 V
Data ConvertersA/D 12x10b; D/A 2x8bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case128-QFP
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantEeprom Size-
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Section 2 Instruction Descriptions
2.2.23 (2)
CMP (W)
CMP (CoMPare)
Operation
Rd – (EAs), set/clear CCR
Assembly-Language Format
CMP.W <EAs>, Rd
Operand Size
Word
Description
This instruction subtracts the source operand from the contents of a 16-bit register Rd (destination
operand) and sets or clears the condition code bits according to the result. The contents of the 16-
bit register Rd remain unchanged.
Available Registers
Rd: R0 to R7, E0 to E7
Rs: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Addressing
Mnemonic
Mode
Immediate
CMP.W
Register direct
CMP.W
Notes
Rev. 4.00 Feb 24, 2006 page 92 of 322
REJ09B0139-0400
Condition Code
I
H: Set to 1 if there is a borrow at bit 11;
otherwise cleared to 0.
N: Set to 1 if the result is negative; otherwise
cleared to 0.
Z: Set to 1 if the result is zero; otherwise
cleared to 0.
V: Set to 1 if an overflow occurs; otherwise
cleared to 0.
C: Set to 1 if there is a borrow at bit 15;
otherwise cleared to 0.
Instruction Format
Operands
1st byte
2nd byte
#xx:16, Rd
7
9
2
Rs, Rd
1
D
rs
Compare
UI H
U
N
Z
V
3rd byte
4th byte
rd
IMM
rd
C
No. of
States
2
1