MC68HC908LB8CPE Freescale Semiconductor, MC68HC908LB8CPE Datasheet
MC68HC908LB8CPE
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MC68HC908LB8 Data Sheet M68HC08 Microcontrollers MC68HC908LB8 Rev. 1 8/2005 freescale.com ...
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... Revision Date Level 1/2005 0 First release 8/2005 1 Section Minor changes to the second and third paragraphs in the note in Section 10.4.9 Deadtime Freescale Semiconductor Revision History Description 4.7 Application Information added. Insertion. MC68HC908LB8 Data Sheet, Rev. 1 Page Number(s) N/A 56 101 ...
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... MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
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... Chapter 15 Pulse Width Modulator with Fault Input (PWM 141 Chapter 16 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Chapter 17 System Integration Module (SIM .171 Chapter 18 Timer Interface Module (TIM .187 Chapter 19 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Chapter 20 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 Chapter 21 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . 231 Freescale Semiconductor MC68HC908LB8 Data Sheet, Rev ...
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... MC68HC908LB8 Data Sheet Freescale Semiconductor ...
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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2 Features 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.4 Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.4 Monotonicity Freescale Semiconductor Chapter 1 General Description Chapter 2 Memory Chapter 3 Analog-to-Digital Converter (ADC) MC68HC908LB8 Data Sheet, Rev ...
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... COPD (COP Disable 6.3.7 COPRS (COP Rate Select 6.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8 Chapter 4 Op Amp/Comparator Module Chapter 5 Configuration Register (CONFIG) Chapter 6 MC68HC908LB8 Data Sheet Freescale Semiconductor ...
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... I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9.7.1 Keyboard Status and Control Register 9.7.2 Keyboard Interrupt Enable Register 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.2 Features Freescale Semiconductor Chapter 7 Central Processor Unit (CPU) Chapter 8 External Interrupt (IRQ) Chapter 9 Keyboard Interrupt Module (KBI) Chapter 10 High Resolution PWM (HRP) MC68HC908LB8 Data Sheet ...
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... Computer Operating Properly Module (COP 114 11.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.6 External Interrupt Module (IRQ 114 11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.7 Keyboard Interrupt Module (KBI 115 10 Chapter 11 Low-Power Modes MC68HC908LB8 Data Sheet Freescale Semiconductor ...
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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.2 Features 123 13.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.3.1 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.3.1.1 Internal Oscillator Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.3.1.2 Internal to External Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.3.2 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Freescale Semiconductor Chapter 12 Low-Voltage Inhibit (LVI) Chapter 13 Oscillator Module (OSC) MC68HC908LB8 Data Sheet 11 ...
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... Timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 15.3.1 Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 15.3.2 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 15.4 PWM Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 15.4.1 Load Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 15.4.2 PWM Data Overflow and Underflow Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 15.4.3 Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15.5 Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12 Chapter 14 Input/Output (I/O) Ports Chapter 15 MC68HC908LB8 Data Sheet Freescale Semiconductor ...
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... IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 16.3.2.4 Timer Interface Module (TIM 170 16.3.2.5 KBD0–KBD6 Pins 170 16.3.2.6 Analog-to-Digital Converter (ADC 170 16.3.2.7 Pulse-Width Modulator with Fault Input (PWM 170 16.3.2.8 High Resolution PWM (HRP 170 Freescale Semiconductor Chapter 16 Resets and Interrupts MC68HC908LB8 Data Sheet 13 ...
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... Output Compare 190 18.3.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 18.3.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 18.3.4 Pulse Width Modulation (PWM 191 18.3.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 14 Chapter 17 System Integration Module (SIM) Chapter 18 Timer Interface Module (TIM) MC68HC908LB8 Data Sheet Freescale Semiconductor ...
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... Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 19.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 19.3.1.6 Baud Rate 215 19.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 19.3.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 20.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 20.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Freescale Semiconductor Chapter 19 Development Support Chapter 20 Electrical Specifications MC68HC908LB8 Data Sheet 15 ...
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... Ordering Information and Mechanical Specifications 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 21.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 21.3 20-Pin Small Outline Integrated Circuit (SOIC) Package — Case #751D . . . . . . . . . . . . . . . . 232 21.4 20-Pin Plastic Dual In-Line Package (PDIP) — Case #738 232 16 Chapter 21 MC68HC908LB8 Data Sheet Freescale Semiconductor ...
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... Three shared with high resolution PWM (HRP) – Three shared with PWM module 1. No security feature is absolutely secure. However, Freescale Semiconductor’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor MC68HC908LB8 Data Sheet, Rev ...
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... Master reset pin and power-on reset (POR) • 674 bytes of FLASH programming routines read-only memory (ROM) • Break module (BRK) to allow single breakpoint setting during in-circuit debugging • Internal pullup on RST pin to reduce customer system cost 18 MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
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... Fast 16/8 divide instruction • Binary coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908LB8. Freescale Semiconductor MC68HC908LB8 Data Sheet, Rev. 1 MCU Block Diagram 19 ...
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... Figure 1-1. MCU Block Diagram MC68HC908LB8 Data Sheet, Rev. 1 (1) PTA6 /AD5/TCH0/KBI6 (1) PTA5 /RST/KBI5 (1) PTA4 /AD4/KBI4 (1) PTA3 /AD3/KBI3 (1) PTA2 /AD2/KBI2 (1) PTA1 /AD1/KBI1 (1) PTA0 /AD0/KBI0 (2) PTB7/V /AD6/FAULT OUT PTB6/V– PTB5/V+ PTB4/PWM1 PTB3/PWM0 (2) PTB2/FAULT PTB1/BOT PTB0/TOP (1) PTC2 /SHTDWN/IRQ (1) PTC1 /OSC2 (1) PTC0 /OSC1 Freescale Semiconductor ...
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... PTA4 — General purpose I/O port PTA4 KBI4 — Keyboard interrupt input 4 ADC4 — A/D channel 4 input PTA5 — General purpose I/O port PTA5 RST — Reset input, active low with internal pullup and Schmitt trigger KBI5 — Keyboard interrupt input 5 Freescale Semiconductor PTA6/ADC5/TCH0/KBI6 ...
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... Table 1-1. Pin Functions (Continued) Description NOTE MC68HC908LB8 Data Sheet, Rev. 1 Input/Output Input/Output Input Input/Output Input Input/Output Output Input/Output Output Input/Output Input Input/Output Output Input/Output Output Input/Output Input Input/Output Input Input/Output Output Input Input Input/Output Input Input/Output Output Output Input Input Input Freescale Semiconductor ...
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... Any unused inputs and I/O ports should be tied to an appropriate logic level (either require termination, termination is recommended to reduce the possibility of static damage. Freescale Semiconductor Highest-to-Lowest Priority Sequence ADC0 → KBI0 → PTA0 ADC1 → KBI1 → PTA1 ADC2 → KBI2 → PTA2 ADC3 → KBI3 → PTA3 ADC4 → ...
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... An external clock source – An external RC oscillator – The internal oscillator 24 PWM SIM BUSCLKX4 BUSCLKX4 BUSCLKX2 ÷2 BUSCLK ÷4 CPU FLASH Figure 1-3 MC68HC908LB8 Data Sheet, Rev. 1 HRP COP TIM ADC KBI FLASH PROGRAMMING RAM MON ROM ROM shows a simplified clock Freescale Semiconductor ...
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... BRKH • $FE0A; break address register low, BRKL • $FE0B; break status and control register, BRKSCR • $FE0C; LVI status register, LVISR • $FF7E; FLASH block protect register, FLBPR Freescale Semiconductor MC68HC908LB8 Data Sheet, Rev. 1 Figure 2-1, includes: 25 ...
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... INTERRUPT STATUS REGISTER 2 (INT2) RESERVED RESERVED FLASH CONTROL REGISTER (FLCR) BREAK ADDRESS REGISTER HIGH (BRKH) BREAK ADDRESS REGISTER LOW (BRKL) BREAK STATUS AND CONTROL REGISTER (BRKSCR) LVI STATUS REGISTER (LVISR) UNIMPLEMENTED Figure 2-1. Memory Map MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
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... Reset: Read: Data Direction Register B $0005 (DDRB) Write: See page 137. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor MONITOR ROM 350 BYTES FLASH BLOCK PROTECT REGISTER (FLBPR) UNIMPLEMENTED INTERNAL OSCILLATOR TRIM VALUE UNIMPLEMENTED FLASH VECTORS 34 BYTES Figure 2-1. Memory Map (Continued) ...
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... One-time writable register after reach reset. = Unimplemented R Bold = Buffered U = Unaffected MC68HC908LB8 Data Sheet, Rev Bit DDRC1 DDRC0 PTA3PUE PTA2PUE PTA1PUE PTA0PUE PTCPUE2 PTCPUE1 PTCPUE0 KEYF 0 IMASKK MODEK ACKK KBIE3 KBIE2 KBIE1 KBIE0 IRQF 0 IMASK MODE ACK RSTEN ( SSREC STOP COPD Reserved Freescale Semiconductor ...
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... Register High (TCH1H) Write: See page 201. Reset: Read: Timer Channel 1 $002A Register Low (TCH1L) Write: See page 201. Reset: $002B ↓ Unimplemented $0029 Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit TOF 0 TOIE TSTOP 0 TRST Bit 15 14 ...
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... U U COCO AIEN ADCO ADCH4 AD7 AD6 AD5 AD4 Unaffected by reset 0 ADIV2 ADIV1 ADIV0 Unimplemented R Bold = Buffered U = Unaffected MC68HC908LB8 Data Sheet, Rev Bit 0 EGGST R R ECGON TRIM3 TRIM2 TRIM1 TRIM0 OACE ADCH3 ADCH2 ADCH1 ADCH0 AD2 AD1 AD0 Reserved Freescale Semiconductor ...
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... Read: PWM 0 Value Register Low $004A (PVAL0L) Write: See page 155. Reset: Read: PWM 1 Value Register High $004B (PVAL1H) Write: See page 154. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit FPOS PWMINT PWMF LDFQ1 LDFQ0 DIS1 ...
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... Buffered U = Unaffected MC68HC908LB8 Data Sheet, Rev Bit 0 Bit 3 Bit 2 Bit 1 Bit MAP1 MAP0 HRP- SHTIE SHTEN HRPEN (1) MODE DC6 DC5 DC4 DC3 STEP3 STEP3 STEP1 STEP0 STEP3 STEP2 STEP1 STEP0 DT3 DT2 DT1 DT0 TB11 TB10 TB9 TB8 Reserved Freescale Semiconductor ...
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... See page 37. Reset: Read: Break Address Register High $FE09 (BRKH) Write: See page 206. Reset: Read: Break Address Register Low $FE0A (BRKL) Write: See page 206. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit TB7 TB6 TB5 TB4 ...
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... Factory programmed FLASH byte BPR7 BPR6 BPR5 BPR4 Unaffected by reset Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented R Bold = Buffered U = Unaffected MC68HC908LB8 Data Sheet, Rev TRIM3 TRIM2 TRIM1 Reserved BPR3 BPR2 BPR1 = Reserved Freescale Semiconductor Bit TRIM0 BPR0 ...
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... Highest Lowest 2.5 Random-Access Memory (RAM) Addresses $0080 through $00FF are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. Freescale Semiconductor . Table 2-1. Vector Addresses Address Vector $FFFF ...
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... It is recommended that the user utilize the FLASH programming routines provided in the on-chip ROM, which are described more fully in a separate Freescale Semiconductor application note. The FLASH memory is an array of 8 Kbytes with an additional 34 bytes of user vectors and one byte of block protection ...
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... Any FLASH memory page can be erased alone, except for the 34-byte interrupt vectors page, which must be mass erased security feature is absolutely secure. However, Freescale Semiconductor’s strategy is to make reading or copying the FLASH difficult for unauthorized users. ...
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... Wait for a time, t NVHL 1. When in monitor mode, with security sequence failed (see of any FLASH address. 38 NOTE CAUTION (1) within the FLASH memory address range. NOTE 19.3.2 Security), write to the FLASH block protect register instead MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
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... This program sequence is repeated throughout the memory until all data is programmed. 1. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing PGM bit, must not exceed the maximum programming time, t Freescale Semiconductor NOTE CAUTION NOTE NOTE maximum ...
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... Therefore, if this page is not protected by FLBPR the register is erased by either a page or mass erase operation. 40 NOTE maximum, see PROG maximum defined as the cumulative high voltage HV HV must satisfy this condition 32) <= t maximum PGS PROG HV CAUTION NOTE NOTE MC68HC908LB8 Data Sheet, Rev. 1 20.12 Freescale Semiconductor ...
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... PROG This row program algorithm assumes the row programmed are initially erased. Figure 2-4. FLASH Programming Flowchart Freescale Semiconductor 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS ...
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... FFFF $FF40 (1111 1111 0100 0000) — $FFFF FLBPR and vectors are protected $FF80 (1111 1111 1000 0000) — FFFF Vectors are protected The entire FLASH memory is not protected. MC68HC908LB8 Data Sheet, Rev Bit 0 BPR2 BPR1 BPR0 Freescale Semiconductor ...
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... FLASH, otherwise the operation will discontinue, and the FLASH will be on standby mode Standby mode is the power saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH minimum. Freescale Semiconductor NOTE MC68HC908LB8 Data Sheet, Rev. 1 FLASH Memory (FLASH) ...
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... Memory 44 MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
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... DD POWER V SS Notes: 1. Pin contains integrated pullup device. 2. Fault function switchable between pins PTB2 and PTB7. Figure 3-1. Block Diagram Highlighting ADC Block and Pins Freescale Semiconductor INTERNAL BUS DUAL CHANNEL PWM MODULE HIGH RESOLUTION PWM MODULE LOW-VOLTAGE INHIBIT MODULE COMPUTER OPERATING ...
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... ADC channels. The channel select bits define which ADC channel/port pin will be used as 46 DDRAx/DDRAx RESET PTAx/PTBx ADC DATA REGISTER COMPLETE ADC ADC CLOCK CLOCK GENERATOR ADIV[2:0] Figure 3-2. ADC Block Diagram MC68HC908LB8 Data Sheet, Rev. 1 DISABLE PTAx/PTBx ADC CHANNEL x DISABLE ADC VOLTAGE IN ADCH[4: CHANNEL ADIN SELECT Freescale Semiconductor ...
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... When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC conversion. A CPU interrupt is generated if the COCO bit The COCO bit is not used as a conversion complete flag when interrupts are enabled. Freescale Semiconductor , the ADC converts the signal to $FF (full scale). If the REFH and V respectively ...
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... ADSCR is written or whenever the ADR is read. If the AIEN bit the COCO becomes a read/write bit, which should be cleared to 0 for CPU to service the ADC interrupt request. Reset clears this bit AIEN ADCO ADCH4 ADCH3 MC68HC908LB8 Data Sheet, Rev Bit 0 ADCH2 ADCH1 ADCH0 Freescale Semiconductor ...
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... The voltage levels supplied from internal reference nodes, as specified in Table 3-1, are used to verify the operation of the ADC converter both in production test and for user applications. ADCH4 ADCH3 ↓ ↓ Freescale Semiconductor Table 3-1. NOTE Table 3-1. Mux Channel Select ADCH2 ADCH1 ADCH0 ↓ ...
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... Table 3-2. ADC Clock Divide Ratio ADIV1 ADIV0 ADC Clock Rate ADC input clock ÷ ADC input clock ÷ ADC input clock ÷ ADC input clock ÷ ADC input clock ÷ 16 (1) ( MC68HC908LB8 Data Sheet, Rev. 1 respectively. SS AD2 AD1 AD0 2 1 Bit Freescale Semiconductor ...
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... The ADC requires a clock rate of approximately 1 MHz for correct operation. If the selected clock source is not fast enough, the ADC will generate incorrect conversions. See Freescale Semiconductor Bus frequency ≅ 1 MHz f = ADIC ADIV[2:0] MC68HC908LB8 Data Sheet, Rev. 1 I/O Registers 20.8 5.0-Volt ADC Characteristics ...
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... Analog-to-Digital Converter (ADC) 52 MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
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... The op amp/comparator shares two input pins and an output pin with the port B input/output (I/O). The full names of the op amp/comparator pins are listed in Table 4-1. Note that the generic pin names appear in the text that follows. Generic Pin Name Freescale Semiconductor Table 4-1. Pin Name Conventions Full Pin Name V PTB7/V ...
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... OUT MC68HC908LB8 Data Sheet, Rev. 1 (1) PTA6 /AD5/TCH0/KBI6 (1) PTA5 /RST/KBI5 (1) PTA4 /AD4/KBI4 (1) PTA3 /AD3/KBI3 (1) PTA2 /AD2/KBI2 (1) PTA1 /AD1/KBI1 (1) PTA0 /AD0/KBI0 (2) PTB7/V /AD6/FAULT OUT PTB6/V– PTB5/V+ PTB4/PWM1 PTB3/PWM0 (2) PTB2/FAULT PTB1/BOT PTB0/TOP (1) PTC2 /SHTDWN/IRQ (1) PTC1 /OSC2 (1) PTC0 /OSC1 Freescale Semiconductor ...
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... There is a single operational control register (OACCR) that contains the enable bit for the op amp/comparator. Address: $0039 Bit 7 Read: OACM Write: Reset Unimplemented Figure 4-3. Op Amp/Comparator Control Register (OACCR) OACM — Op Amp/Comparator Mode Select Bit This bit selects between 2 modes of operation, op amp mode and comparator mode amp mode selected Freescale Semiconductor OACE OACE + OACE - Unaffected MC68HC908LB8 Data Sheet, Rev ...
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... Use the circuit component values suggested for the common amplfier configurations shown in the following figures (Figure Vin Figure 4-4. Suggested Application Circuit for Unity Gain Buffer 56 NOTE 4-4, Figure 4-5, and Figure 4-6). VDD Unity Gain Buffer + – CL 500pF MC68HC908LB8 Data Sheet, Rev. 1 Vout RL >20kΩ Freescale Semiconductor ...
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... C1 1µF R2 100k R3 Vin 10k Figure 4-5. Suggested Application Circuit for Inverting Amplifier Vin VDD R1 100k C1 R2 1µF 100k Figure 4-6. Suggested Application Circuit for Non-inverting Amplifier Freescale Semiconductor VDD R1 100k Inverting Amplifier + – R4 >50k VDD C2 1µF R5 100k Non-inverting Amplifier R6 + 100k – ...
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... Op Amp/Comparator Module 58 MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
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... On a FLASH device, the options are one-time writable by the user after each reset. The CONFIG registers are not in the FLASH memory but are special registers containing one-time writable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 5-1 Freescale Semiconductor – – ...
Page 60
... The RSTEN bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaffected IRQEN R OSCOPT1 OSCOPT0 Reserved Oscillator Selection 00 Internal oscillator 01 External oscillator 10 External RC oscillator 11 External XTAL oscillator NOTE MC68HC908LB8 Data Sheet, Rev Bit RSTEN Unaffected DD Freescale Semiconductor ...
Page 61
... MCU is not protected from a low-power condition. However, when using the short stop recovery configuration option, the 32-BUSCLKX4 delay must be greater than the LVI’s turn on time to avoid a period in startup where the LVI is not protecting the MCU. Freescale Semiconductor 6 5 ...
Page 62
... STOP enables the STOP instruction STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. See 1 = COP module disabled 0 = COP module enabled 62 Chapter 6 Computer Operating Properly (COP) MC68HC908LB8 Data Sheet, Rev. 1 Module. Freescale Semiconductor ...
Page 63
... COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SELECT (COPRS FROM CONFIG1) 1. See Chapter 17 System Integration Module (SIM) Freescale Semiconductor SIM MODULE 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER for more details. ...
Page 64
... A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the SIM counter – 2 BUSCLKX4 cycle overflow option, using the internal clock to NOTE Register. NOTE Figure 6.4 COP Control MC68HC908LB8 Data Sheet, Rev. 1 6-1. Register) clears the COP Freescale Semiconductor ...
Page 65
... To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction. When the STOP bit in the configuration register has the STOP instruction disabled, execution of a STOP instruction results in an illegal opcode reset. Freescale Semiconductor (CONFIG). (CONFIG). ...
Page 66
... Computer Operating Properly (COP) Module 66 MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 67
... Central Processor Unit (CPU) 7.1 Introduction The M68HC08 CPU (central processor unit enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Freescale Semiconductor document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 7.2 Features Features of the CPU include: • ...
Page 68
... CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers Unaffected by reset Figure 7-2. Accumulator ( Figure 7-3. Index Register (H:X) MC68HC908LB8 Data Sheet, Rev Bit 0 Bit Freescale Semiconductor ...
Page 69
... Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. Freescale Semiconductor ...
Page 70
... Negative result 0 = Non-negative result Z — Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00 Zero result 0 = Non-zero result NOTE MC68HC908LB8 Data Sheet, Rev Bit Freescale Semiconductor ...
Page 71
... Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Freescale Semiconductor document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU. ...
Page 72
... DIR (b0 DIR (b1 DIR (b2 DIR (b3 – – – – – – DIR (b4 DIR (b5 DIR (b6 DIR (b7 – – – – – – REL 25 rr – – – – – – REL 27 rr – – – – – – REL 90 rr Freescale Semiconductor ...
Page 73
... BPL rel Branch if Plus BRA rel Branch Always BRCLR n,opr,rel Branch if Bit Clear BRN rel Branch Never BRSET n,opr,rel Branch if Bit Set Freescale Semiconductor Description ⊕ PC ← (PC rel ? ( – – – – – – REL PC ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ← ...
Page 74
... IMM 65 ii ii+1 – – DIR 75 dd IMM A3 ii DIR B3 dd EXT IX2 – – IX1 SP1 9EE3 ff SP2 9ED3 – – INH 72 DIR INH 4B rr – – – – – – INH 5B rr IX1 SP1 9E6B ff rr Freescale Semiconductor ...
Page 75
... LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX Logical Shift Left LSL opr,X (Same as ASL) LSL ,X LSL opr,SP Freescale Semiconductor Description M ← (M) – ← (A) – ← (X) – ← (M) – ← (M) – ← (M) – ← (H:A)/(X) H ← Remainder ⊕ A ← ← ...
Page 76
... INH 88 DIR 39 dd INH 49 INH 59 – – IX1 SP1 9E69 ff DIR 36 dd INH 46 INH 56 – – IX1 SP1 9E66 ff – – – – – – INH 9C INH 80 – – – – – – INH 81 Freescale Semiconductor ...
Page 77
... Test for Negative or Zero TST opr,X TST ,X TST opr,SP TSX Transfer SP to H:X TXA Transfer TXS Transfer H Freescale Semiconductor Description A ← (A) – (M) – (C) C ← ← ← (A) (M ← (H:X) I ← 0; Stop Processing M ← (X) A ← (A) – (M) PC ← (PC Push (PCL) SP ← ...
Page 78
... Logical AND | Logical OR ⊕ Logical EXCLUSIVE Contents of –( ) Negation (two’s complement) # Immediate value « Sign extend ← Loaded with ? If : Concatenated with Set or cleared — Not affected MC68HC908LB8 Data Sheet, Rev. 1 Effect on CCR – – 0 – – – INH 8F Freescale Semiconductor 1 ...
Page 79
Bit Manipulation Branch DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR 1 INH ...
Page 80
... Central Processor Unit (CPU) 80 MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 81
... The external interrupt pin is falling-edge triggered and is software-configurable to be either falling-edge or falling-edge and low-level triggered. The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin. When an interrupt pin is edge-triggered only, the interrupt remains set until a vector fetch, software clear, or reset occurs. Freescale Semiconductor MC68HC908LB8 Data Sheet, Rev ...
Page 82
... Figure 8-1. IRQ Module Block Diagram NOTE Bit Unimplemented Figure 8-2. IRQ I/O Register Summary MC68HC908LB8 Data Sheet, Rev CPU FOR BIL/BIH INSTRUCTIONS IRQF SYNCHRO- IRQ NIZER INTERRUPT REQUEST HIGH TO MODE VOLTAGE SELECT DETECT LOGIC IRQF 0 IMASK ACK Freescale Semiconductor Bit 0 MODE 0 ...
Page 83
... The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR: • Shows the state of the IRQ flag • Clears the IRQ latch • Masks IRQ interrupt request Freescale Semiconductor NOTE is connected to the IRQ pin; this can be DD (BRK). MC68HC908LB8 Data Sheet, Rev. 1 IRQ Module During Break Interrupts 83 ...
Page 84
... MODE — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only IRQF MC68HC908LB8 Data Sheet, Rev Bit 0 0 IMASK MODE ACK Freescale Semiconductor ...
Page 85
... DD POWER V SS Notes: 1. Pin contains integrated pullup device. 2. Fault function switchable between pins PTB2 and PTB7. Figure 9-1. Block Diagram Highlighting KBI Block and Pins Freescale Semiconductor INTERNAL BUS DUAL CHANNEL PWM MODULE HIGH RESOLUTION PWM MODULE LOW-VOLTAGE INHIBIT MODULE COMPUTER OPERATING ...
Page 86
... Register (INTKBIER) Write: See page 90. Reset: 86 ACKK V DD CLR MODEK Bit KBIE6 KBIE5 Unimplemented Figure 9-3. I/O Register Summary MC68HC908LB8 Data Sheet, Rev. 1 KEYF SYNCHRONIZER IMASKK KEYF 0 IMASKK ACKK KBIE4 KBIE3 KBIE2 KBIE1 Freescale Semiconductor KEYBOARD INTERRUPT REQUEST Bit 0 MODEK 0 KBIE0 0 ...
Page 87
... Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin input, overriding the data direction register. However, the data direction register bit must for software to read the pin. Freescale Semiconductor NOTE MC68HC908LB8 Data Sheet, Rev. 1 Functional Description 87 ...
Page 88
... To protect the latch during the break state, write the BCFE bit. With BCFE at 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. See 88 9.7.1 Keyboard Status and Control MC68HC908LB8 Data Sheet, Rev. 1 Register. Freescale Semiconductor ...
Page 89
... This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only 9.7.2 Keyboard Interrupt Enable Register The keyboard interrupt enable register enables or disables each port A pin to operate as a keyboard interrupt pin. Freescale Semiconductor ...
Page 90
... Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register PTAx pin enabled as keyboard interrupt pin 0 = PTAx pin not enabled as keyboard interrupt pin KBIE6 KBIE5 KBIE4 KBIE3 MC68HC908LB8 Data Sheet, Rev Bit 0 KBIE2 KBIE1 KBIE0 Freescale Semiconductor ...
Page 91
... Pin Name Conventions The HRP shares two output pins with two port B input/output (I/O) pins and one input pin with one port C input pin. HRP Generic Pin Name Freescale Semiconductor Figure 10-1, and a block diagram of the HRP module is Table 10-1. Pin Naming Conventions ...
Page 92
... OP AMP/COMPARATOR MODULE NOTE MC68HC908LB8 Data Sheet, Rev. 1 (1) PTA6 /AD5/TCH0/KBI6 (1) PTA5 /RST/KBI5 (1) PTA4 /AD4/KBI4 (1) PTA3 /AD3/KBI3 (1) PTA2 /AD2/KBI2 (1) PTA1 /AD1/KBI1 (1) PTA0 /AD0/KBI0 (2) PTB7/V /AD6/FAULT OUT PTB6/V– PTB5/V+ PTB4/PWM1 PTB3/PWM0 (2) PTB2/FAULT PTB1/BOT PTB0/TOP (1) PTC2 /SHTDWN/IRQ (1) PTC1 /OSC2 (1) PTC0 /OSC1 Freescale Semiconductor ...
Page 93
... When HRPMODE = 0, STEP[4:0] are mapped into the five least significant bits of the HRPPERL register. When HRPMODE = 1, STEP[4:0] are mapped into the five least significant bits of the HRPDCL register. 10.4 Functional Description Figure 10-3 provides a block diagram of the module. Freescale Semiconductor Bit SHTLVL HRPOE 0 ...
Page 94
... The equivalent average frequency over time is 13 kHz. 94 DEADTIME GENERATOR DUAL FREQUENCY GENERATOR DEADTIME GENERATOR DITHERING CONTROLLER MC68HC908LB8 Data Sheet, Rev. 1 HRPCLK TOP BOT COMPLEMENTARY OUTPUTS WITH PROGRAMMABLE DEADTIME SHUTDOWN DETECT INPUT FOR FAST DISABLING OF OUTPUTS SHTDWN Figure 10-4 a signal switches Freescale Semiconductor ...
Page 95
... In this example, the Period signal is output for 25% of the time, i. the 32 steps, and the Period+1 signal is output for 75% of the time, i. the 32 steps. Freescale Semiconductor 1 CYCLE 10 kHz ...
Page 96
... PERIOD1 and DUTY1 define the frequency output by the dual-frequency generator; PERIOD2 and DUTY2 define a second output frequency, which is automatically calculated by the HRP module. The module switches between PERIOD1/DUTY1 and PERIOD2/DUTY2. 96 PERIOD = $80 FREQUENCY = 1/ ($80 * 125 ns) = 62.500 kHz PERIOD = $ MC68HC908LB8 Data Sheet, Rev STEPS 0 Freescale Semiconductor ...
Page 97
... HRPMODE bit, the five least significant bits in the HRPPERL or HRPDCL registers. HRPMODE Mode Variable 0 Frequency Variable Duty 1 Cycle For more detailed information, see Freescale Semiconductor Table 10-2. HRPMODE Bit Options PERIOD1 PERIOD2 P[10:0] P[10:0] +1 P[10:0] P[10:0] 10.4.7 Dithering Controller. MC68HC908LB8 Data Sheet, Rev. 1 ...
Page 98
STEP[4:0] DIVIDER COMPARE INCREMENT 1 5-BIT SEL[2:0] COUNTER 0 COMPARE MODULUS HRPCLK CLK SRC DITHERING TIMEBASE CLKSEL = 0, clock from dual frequency generator CLKSEL = 1, clock from 16-bit timebase counter Figure 10-6. Dithering Controller and Dual Frequency Generator ...
Page 99
... The scaled value in STEP[4:0] (the five least significant bits of HRPDCH:HRPDCL) specifies how many of the selected number of steps are spent on the longer duty cycle, DUTY2. For more detailed information, see Freescale Semiconductor lists the period and duty cycle values based on the HRPMODE bit. Controller. ...
Page 100
... HRPCLK DUTY1 = DC[10:0] P[10:0] = PERIOD1 = ----------------------- - HRPCLK = DUTY1 + 1 = DC[10: Table 10-3 lists the available options. Note that the scaling of the Number of Steps Divide STEP[4:0] by... Reserved Reserved MC68HC908LB8 Data Sheet, Rev ⎞ ⎠ (EQ 10-6) (EQ 10-7) (EQ 10-8) (EQ 10-9) (EQ 10-10 Reserved Reserved Freescale Semiconductor ...
Page 101
... Figure 10-7 shows the relationship between the TOP and BOT input signals to the deadtime generators, the HRPDT register contents, and the outputs from the deadtime generators. Freescale Semiconductor for more detailed information on the HRPMODE bit. Thus, by Table 10-4. Dithering Timebase Options ...
Page 102
... The duty cycle refers to the high level on BOT. Similarly, if the deadtime is equal to or greater than the period minus the duty cycle value, the TOP output will remain at logic 0, while BOT will output a PWM signal. (See 102 DT[7:0] DT[7:0] NOTE Figure 10-9.) MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 103
... DEADTIME BOT 0 Figure 10-8. Deadtime Equal to or Greater Than Duty Cycle DUTY CYCLE = 11 DEADTIME TOP DEADTIME BOT 0 Figure 10-9. Deadtime Equal to or Less Than Period Minus Duty Cycle Freescale Semiconductor PERIOD = 16, DEADTIME = 4 DUTY CYCLE = 4 DEADTIME DEADTIME PERIOD = 16, DEADTIME = 4 DUTY CYCLE = 12 DEADTIME ...
Page 104
... Input/Output Signals Port B shares two of its pins with the HRP. The two output pins are PTB0/TOP and PTB1/BOT. Port C shares one of its pins (PTC2/SHTDWN/IRQ) with the HRP. 104 NOTE NOTE 19.2.2.5 Break Flag Control Register. MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 105
... SHTIE — SHTDWN Interrupt Enable This read/write bit enables HRP CPU interrupt service requests for the SHTDWN pin. Reset clears the SHTIE bit SHTDWN CPU interrupt requests enabled 0 = SHTDWN CPU interrupt requests disabled SHTEN — Shutdown Pin Enable Freescale Semiconductor SHTLVL ...
Page 106
... Writes to the high byte (HRPDCH) are stored in a latch until the low byte (HRPDCL) is written. Both registers are then updated simultaneously. This prevents glitches in the output duty cycle. 106 NOTE NOTE [ ⎛ STEP 4:0 INT ---------------------------- - ⎝ SEL[2: 10 ------------------------- + ------------------------------------------------- - HRPCLK 32 ------------------ - ¥ HRPCLK SEL[2:0] 2 MC68HC908LB8 Data Sheet, Rev ⎞ ⎠ (EQ 10-11) Freescale Semiconductor ...
Page 107
... Writes to the high byte (HRPPERH) are stored in a latch until the low byte (HRPPERL) is written. Both registers are then updated simultaneously. This prevents glitches in the output period. Address: HRPPERH — $0054 Bit 15 Read: P10 Write: Reset: 0 Bit 7 Figure 10-12. HRP Period Registers (HRPPERH:HRPPERL) Freescale Semiconductor HRPDCL — $0053 DC9 DC8 DC7 DC6 0 ...
Page 108
... DT6 DT5 DT4 DT3 HRPTBH:HRPTBL = ------------------------------------------------- - HRPCLK HRPTBL — $0058 TB14 TB13 TB12 TB11 TB6 TB5 TB4 TB3 MC68HC908LB8 Data Sheet, Rev. 1 STEP2 STEP1 STEP0 (EQ 10-14 Bit 0 DT2 DT1 DT0 (EQ 10-15 Bit 8 TB10 TB9 TB8 Bit 0 TB2 TB1 TB0 Freescale Semiconductor ...
Page 109
... These read/write bits select the number of steps used by the dithering counter and set the scaling factor for the STEP[4:0] bits. SEL[2: ( NOTES dithering occurs for this setting. Freescale Semiconductor CLKSRC 0 Table 10-5 Clock Source Dual Frequency Generator 16 bit timebase Table 10-6 Number of Steps Divide STEP[4:0] by... ...
Page 110
... STEP 4:0 ---------------------------- - INT ⎝ ⎠ SEL[2:0] 2 and 60 = $3C -------------------------------------------- - 32 ------------------ - SEL[2: STEP 4:0 ---------------------------- - = 0.5725 0.5725 ¥ 18.32 MC68HC908LB8 Data Sheet, Rev ⎛ ⎞ STEP 4:0 ---------------------------- - INT ⎝ ⎠ SEL[2: (EQ 10-16) + -------------------------------------------- - ------------------ - ¥ 8 ¥ 10 SEL[2:0] 2 (EQ 10-17 0.5725 (EQ 10-18) = 0.5725 (EQ 10-19) (EQ 10-20 Freescale Semiconductor ...
Page 111
... To achieve a switching frequency of less than 100 Hz, we must use the 16-bit timebase counter as the source for the dithering timebase. Switching Frequency HRPTB To insert a 10 µs deadtime in the output signals, we must calculate the value to store in the HRPDT register from the following equation. i.e. Freescale Semiconductor 3 – 10:0 – ...
Page 112
... High Resolution PWM (HRP) 112 MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 113
... Wait Mode If enabled, the break (BRK) module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if the SBSW bit in the break status register is set. Freescale Semiconductor MC68HC908LB8 Data Sheet, Rev. 1 Chapter 5 113 ...
Page 114
... IRQ CPU interrupt requests to bring the MCU out of wait mode if IRQ function is enabled. 11.6.2 Stop Mode The IRQ module remains active in stop mode. Clearing the IMASK bit in the IRQ status and control register enables IRQ CPU interrupt requests to bring the MCU out of stop mode. 114 MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 115
... LVI module can generate a reset and bring the MCU out of wait mode. 11.9.2 Stop Mode If enabled, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. Freescale Semiconductor NOTE MC68HC908LB8 Data Sheet, Rev. 1 Keyboard Interrupt Module (KBI) ...
Page 116
... The PWM0 and PWM1 outputs are set to logic 0. The STOP instruction does not affect the register conditions or the state of the PWM counters. When the MCU exits stop mode after an external interrupt the PWM resumes operation. 116 MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 117
... PWMINT • High Resolution PWM (HRP) — A CPU interrupt request from the HRP loads the program counter with the contents of: $FFED and $FFEC Freescale Semiconductor MC68HC908LB8 Data Sheet, Rev. 1 Timer Interface Module (TIM) voltage resets TRIPF 117 ...
Page 118
... Setting SSREC reduces stop recovery time from 4096 BUSCLKX4 cycles to 32 BUSCLKX4 cycles. Use the full stop recovery time (SSREC = 0) in applications that use an external crystal. 118 . NOTE MC68HC908LB8 Data Sheet, Rev. 1 voltage resets the TRIPF Freescale Semiconductor ...
Page 119
... LVI module. LVISTOP, LVIPWRD, and LVIRSTD are user selectable options found in the configuration register (CONFIG1). See (CONFIG LOW V DD DETECTOR Freescale Semiconductor voltage falls below the LVI trip falling voltage STOP INSTRUCTION FROM CONFIG LVIRSTD LVIPWRD FROM CONFIG V > ...
Page 120
... LVI will maintain a reset condition until DD TRIPF . This prevents a condition in which the MCU is TRIPR is approximately equal HYS MC68HC908LB8 Data Sheet, Rev. 1 voltage. Clearing the LVI DD falls below a voltage, DD rises above a voltage which TRIPR for the reset recovery greater than TRIPF TRIPR Freescale Semiconductor by polling ...
Page 121
... When the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration register is set, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. Freescale Semiconductor voltage was detected below the V DD ...
Page 122
... Low-Voltage Inhibit (LVI) 122 MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 123
... External crystal: A built-in oscillator module (XTAL oscillator) that requires an external crystal or ceramic-resonator. 13.3 Functional Description The oscillator contains these major subsystems: • Internal oscillator circuit • Internal or external clock switch control • External clock circuit • External crystal circuit • External RC clock circuit Freescale Semiconductor MC68HC908LB8 Data Sheet, Rev. 1 123 ...
Page 124
... Chapter 14 Input/Output (I/O) MC68HC908LB8 Data Sheet, Rev. 1 (1) PTA6 /AD5/TCH0/KBI6 (1) PTA5 /RST/KBI5 (1) PTA4 /AD4/KBI4 (1) PTA3 /AD3/KBI3 (1) PTA2 /AD2/KBI2 (1) PTA1 /AD1/KBI1 (1) PTA0 /AD0/KBI0 (2) PTB7/V /AD6/FAULT OUT PTB6/V– PTB5/V+ PTB4/PWM1 PTB3/PWM0 (2) PTB2/FAULT PTB1/BOT PTB0/TOP (1) PTC2 /SHTDWN/IRQ (1) PTC1 /OSC2 (1) PTC0 /OSC1 Ports. Freescale Semiconductor ...
Page 125
... BUSCLKX4 and also divided by two to create BUSCLKX2. In this configuration, the OSC2 pin cannot output BUSCLKX4. So the OSC2EN bit in the port C pullup enable register will be clear to enable PTC1 I/O functions on the pin. Freescale Semiconductor Table 13-2. The oscillator module control logic will NOTE MC68HC908LB8 Data Sheet, Rev ...
Page 126
... In this configuration, the OSC2 pin can be left in the reset state as PTC1. Or, the OSC2EN bit in the port C pullup enable register can be set to enable the OSC2 function on the pin without affecting the clocks. 126 NOTE ) is included in the diagram to follow strict Pierce S MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 127
... FROM SIM SIMOSCEN MCU OSC1 Figure 13-2. XTAL Oscillator External Connections FROM SIM SIMOSCEN EN MCU EXT Figure 13-3. RC Oscillator External Connections Freescale Semiconductor TO SIM BUSCLKX4 BUSCLKX2 XTALCLK ÷ 2 OSC2 R ( Note can be zero (shorted) when used with higher S frequency crystals. Refer to manufacturer’s data ...
Page 128
... PTC1 I/O Controlled by OSC2EN bit in PTCPUE register OSC2EN = 0: PTC1 I/O OSC2EN = 1: BUSCLKX4 output Figure 13-2 shows only the logical relation of XTALCLK to OSC1 shows only the logical relation of RCCLK to OSC1 and may not MC68HC908LB8 Data Sheet, Rev and comes XCLK Freescale Semiconductor ...
Page 129
... All CONFIG2 register bits will have a default configuration. Refer to (CONFIG) for more information on how the CONFIG2 register is used. Table 13-2 shows how the OSCOPT bits are used to select the oscillator clock source. Freescale Semiconductor MC68HC908LB8 Data Sheet, Rev. 1 Low Power Modes 13.3.1.1 Internal Oscillator Chapter 5 Configuration Register ...
Page 130
... This bit is ignored in monitor mode when the internal oscillator is bypassed External clock generator enabled 0 = External clock generator disabled 130 Table 13-2. Oscillator Modes OSCOPT0 Oscillator Modes 0 0 Internal Oscillator 0 1 External Oscillator 1 0 External External Crystal Reserved MC68HC908LB8 Data Sheet, Rev Bit 0 ECGST R ECGON Freescale Semiconductor ...
Page 131
... TRIM = $80). The trimmed frequency is guaranteed not to vary by more than ±5% over the full specified range of temperature and voltage. The reset value is $80, which sets the frequency to 16 MHz (4.0 MHz bus speed) ±25%. Freescale Semiconductor 6 5 ...
Page 132
... Oscillator Module (OSC) 132 MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 133
... Data Direction Register A $0004 (DDRA) Write: See page 135. Reset: Read: Data Direction Register B $0005 (DDRB) Write: See page 137. Reset: Read: Data Direction Register C $0006 (DDRC) Write: See page 139. Reset: Freescale Semiconductor NOTE Bit PTA6 PTA5 PTB7 PTB6 PTB5 DDRA6 DDRA5 ...
Page 134
... OSC2EN Unimplemented PTA6 PTA5 PTA4 Unaffected by reset = Unimplemented Figure 14-2. Port A Data Register (PTA) Chapter 9 Keyboard Interrupt Module (KBI). MC68HC908LB8 Data Sheet, Rev PTA3PUE PTA2PUE PTA1PUE PTCPUE2 PTCPUE1 PTCPUE0 Table 1-1 . Pin Bit 0 PTA3 PTA2 PTA1 PTA0 Freescale Semiconductor Bit 0 PTA0PUE 0 0 ...
Page 135
... When bit DDRAx reading address $0000 reads the PTAx data latch. When bit DDRAx reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. PTAPUE DDRA PTA Bit Bit Bit ( Freescale Semiconductor DDRA6 DDRA5 DDRA4 DDRA3 NOTE DDRAx RESET PTAx V DD ...
Page 136
... B. Reset has no effect on port B data. 136 PTA6PUE PTA5PUE PTA4PUE PTA3PUE PTB6 PTB5 PTB4 PTB3 Unaffected by reset Figure 14-6. Port B Data Register (PTB) MC68HC908LB8 Data Sheet, Rev Bit 0 PTA2PUE PTA1PUE PTA0PUE Table 1-1 . Pin Functions 2 1 Bit 0 PTB2 PTB1 PTB0 Freescale Semiconductor ...
Page 137
... READ PTB ($0001) When bit DDRBx reading address $0001 reads the PTBx data latch. When bit DDRBx reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Freescale Semiconductor ...
Page 138
... Read/Write (2) DDRB7–DDRB0 Output DDRB7–DDRB0 NOTE PTC2 is input only Figure 14-9. Port C Data Register (PTC) MC68HC908LB8 Data Sheet, Rev. 1 Accesses to PTB Read Write (3) Pin PTB7–PTB0 PTB7–PTB0 PTB7–PTB0 Table 1-1 . Pin 2 1 Bit 0 PTC2 PTC1 PTC0 Freescale Semiconductor ...
Page 139
... PTC2. When bit DDRCx reading address $0002 reads the PTCx data latch. When bit DDRCx reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Freescale Semiconductor ...
Page 140
... I/O Pin to DDRC Mode Read/Write (3) DDRC1–DDRC0 Input (5) DDRC1–DDRC0 Input, Hi-Z Output DDRC1–DDRC0 MC68HC908LB8 Data Sheet, Rev. 1 Accesses to PTC (1) Read Write Pin PTC1–PTC0 Pin PTC1–PTC0 PTC2–PTC0 PTC1–PTC0 2 1 Bit 0 PTCPUE2 PTCPUE1 PTCPUE0 Freescale Semiconductor (4) (4) ...
Page 141
... The highest resolution for edge-aligned operation is 125 ns (BUSCLK = 8 MHz). A summary of the PWM registers is shown in 15.2 Features Features of the PWMMC include: • Two independent PWM signals • Edge-aligned PWM signals • PWM signal polarity control • Programmable fault protection Freescale Semiconductor Figure 15-2. Figure 15-3. MC68HC908LB8 Data Sheet, Rev. 1 141 ...
Page 142
... MODULE OP AMP/COMPARATOR MODULE MC68HC908LB8 Data Sheet, Rev. 1 (1) PTA6 /AD5/TCH0/KBI6 (1) PTA5 /RST/KBI5 (1) PTA4 /AD4/KBI4 (1) PTA3 /AD3/KBI3 (1) PTA2 /AD2/KBI2 (1) PTA1 /AD1/KBI1 (1) PTA0 /AD0/KBI0 (2) PTB7/V /AD6/FAULT OUT PTB6/V– PTB5/V+ PTB4/PWM1 PTB3/PWM0 (2) PTB2/FAULT PTB1/BOT PTB0/TOP (1) PTC2 /SHTDWN/IRQ (1) PTC1 /OSC2 (1) PTC0 /OSC1 Freescale Semiconductor ...
Page 143
... See page 157. Fault Control Register $0042 (FCR) See page 159. Fault Status Register $0043 (FSR) See page 159. Fault Control Register 2 $0044 (FCR2) See page 160. Freescale Semiconductor 8 PWM CHANNELS 1 AND 2 12 TIMEBASE Bit Read: 0 FPOS PWMINT Write: Reset: ...
Page 144
... Bit 4 Bit 3 Bit 2 Bit 1 Bit 12 Bit 11 Bit 10 Bit Bit 4 Bit 3 Bit 2 Bit Bit 12 Bit 11 Bit 10 Bit Bit 4 Bit 3 Bit 2 Bit MAP1 Bold = Buffered Freescale Semiconductor Bit 0 Bit 8 0 Bit 0 0 Bit 8 Bit 0 Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 MAP0 1 ...
Page 145
... PWM control register 2 affects the PWM clock frequency. This prescaler is buffered and will not be used by the PWM generator until the LDOK bit is set and a new PWM reload cycle begins. Freescale Semiconductor MODULUS = 4 PERIOD = 4 X (PWM ...
Page 146
... Table 15-1. PWM Prescaler PWM Clock Frequency 00 BUSCLK 01 BUSCLK/2 10 BUSCLK/4 11 BUSCLK/8 Table 15-2. PWM Reload Frequency PWM Reload Frequency 00 Every PWM cycle 01 Every 2 PWM cycles 10 Every 4 PWM cycles 11 Every 8 PWM cycles MC68HC908LB8 Data Sheet, Rev. 1 Table 15-2. When a reload cycle Freescale Semiconductor ...
Page 147
... PWMINT bit is set. To prevent this, the software should clear the PWMINT bit before enabling the PWM module. Setting PWMEN forces PWM1 and PWM0 to be inputs and the appropriately configured FAULT pin output, overriding the data Freescale Semiconductor NOTE RELOAD CHANGE RELOAD ...
Page 148
... LDFQ1:LDFQ0 = 00 (RELOAD EVERY CYCLE) LDOK = 1 LDOK = 1 MODULUS = 4 MODULUS = 2 PWM VALUE = 2 PWM VALUE = 2 PWMF SET PWMF SET Figure MC68HC908LB8 Data Sheet, Rev. 1 LDOK = 0 MODULUS = 3 PWM VALUE = 1 PWMF SET LDOK = 0 MODULUS = 1 PWM VALUE = 2 PWMF SET 15-4, if the PWM value is less than or Freescale Semiconductor ...
Page 149
... A fault can also generate a CPU interrupt. The fault pin has its own interrupt vector. 15.5.1 Fault Condition Input Pin A logic high level on a fault pin disables the PWM(s) determined by the disable map bits (MAPx). The external fault pin is software-configurable to re-enable the PWMs either with the fault pin (automatic Freescale Semiconductor NOTE Condition Normal ...
Page 150
... FTACK bit. 150 CYCLE START FMODE AUTO MODE ONE S Q SHOT FFLAG MANUAL MODE R FINT1 Figure 15-10. PWM Disabling Scheme PWM(S) DISABLED (INACTIVE) MC68HC908LB8 Data Sheet, Rev. 1 FAULT PIN DISABLE S Q PWM DISABLE R INTERRUPT REQUEST PWM(S) ENABLED Freescale Semiconductor ...
Page 151
... PWM pins. The PWM pin(s) remain disabled until the PWM disable bit is cleared and a new PWM cycle begins as shown in Figure 15-13. Setting a PWM disable bit does not latch a CPU interrupt request, and there are no event flags associated with the PWM disable bits. Freescale Semiconductor NOTE Figure 15-12. PWM(S) DISABLED FFLAGX CLEARED MC68HC908LB8 Data Sheet, Rev ...
Page 152
... If an interrupt is issued from the PWM module (via a reload or a fault), the microcontroller will exit wait mode. 152 NOTE 15.8.2 PWM Counter Modulo DRIVE ACCORDING TO PWM VALUE AND POLARITY Figure 15-13. PWMEN and PWM Pins NOTE MC68HC908LB8 Data Sheet, Rev. 1 Registers. PORT FUNCTION Freescale Semiconductor ...
Page 153
... PWM Counter Modulo Registers The PWM counter modulus registers (PMODH and PMODL) hold a 12-bit unsigned number that determines the maximum count for the up-only counter. The PWM period will equal the modulus. See Figure 15-16 and Figure 15-17. Freescale Semiconductor ...
Page 154
... Figure 15-18. PWMx Value Registers High (PVALxH) 154 Bit Bit 6 Bit 5 Bit 4 Bit 3 Indeterminate after reset NOTE Bit 14 Bit 13 Bit 12 Bit Buffered MC68HC908LB8 Data Sheet, Rev Bit 0 Bit 10 Bit 9 Bit 8 Indeterminate after reset 2 1 Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 10 Bit 9 Bit Freescale Semiconductor ...
Page 155
... ADC. PWMINT — PWM Interrupt Enable Bit This read/write bit allows the user to enable and disable PWM CPU interrupts. If set, a CPU interrupt will be pending when the PWMF flag is set Enable PWM CPU interrupts 0 = Disable PWM CPU interrupts Freescale Semiconductor Bit 6 ...
Page 156
... LDOK bit has been set, and a new PWM cycle is starting. The load frequency bits are not used until the current load cycle is complete. See Figure 15-21. The user should initialize this register before enabling the PWM. 156 NOTE NOTE NOTE Bit. NOTE MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 157
... This read/write bit selects the polarity of the PWM waveform of PWM1. Positive polarity means that when the PWM is active the PWM output is high. Conversely, negative polarity means that when the PWM is active the PWM output is low PWM1 has positive polarity 0 = PWM1 has negative polarity Freescale Semiconductor ...
Page 158
... Disables PWM0 when an external fault occurs 0 = Prevents PWM0 from being disabled by hardware 158 NOTE Table 15-5. PWM Prescaler Prescaler Bits PRSC1 and PRSC0 Unimplemented MC68HC908LB8 Data Sheet, Rev. 1 Table PWM Clock Frequency BUSCLK BUSCLK/2 BUSCLK/4 BUSCLK Bit 0 0 MAP1 MAP0 Freescale Semiconductor 15-5. ...
Page 159
... The FFLAG event bit is set immediately when a rising edge is seen on the fault pin. To clear the FFLAG bit, the user must write the FTACK bit in the fault acknowledge register fault has occurred on the fault pin new fault on the fault pin Freescale Semiconductor ...
Page 160
... Edge-aligned mode: The time it takes the PWM counter to count up (modulus/BUSCLK). See Figure 15-26. Figure 15-26. PWM Clock Cycle and PWM Cycle Definition 160 Unimplemented Edge-Aligned Mode PWM CLOCK CYCLE PWM CYCLE (OR PERIOD) MC68HC908LB8 Data Sheet, Rev Bit FTACK Figure 15-26. Freescale Semiconductor ...
Page 161
... Frequency at which new PWM parameters get loaded into the PWM. See LDFQ1:LDFQ0 = 01 — Reload Every Two Cycles RELOAD NEW MODULUS, PRESCALER, & PWM VALUES IF LDOK = 1 Figure 15-27. PWM Load Cycle/Frequency Definition Freescale Semiconductor PWM LOAD CYCLE (1/PWM LOAD FREQUENCY) RELOAD NEW MODULUS, PRESCALER, & PWM VALUES IF LDOK = 1 MC68HC908LB8 Data Sheet, Rev ...
Page 162
... Pulse Width Modulator with Fault Input (PWM) 162 MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 163
... POR. The POR is not a brown-out detector, low-voltage detector, or glitch detector. A power-on reset: • Drives the RST pin low during the oscillator stabilization delay Freescale Semiconductor , generates an external reset when pin PTA5/RST/KB5 is IRL ) to reset the MCU. This distinguishes between a reset and POR MC68HC908LB8 Data Sheet, Rev ...
Page 164
... ILAD bit in the SIM reset status register. A data fetch from an unmapped address does not generate a reset. 164 4096 32 CYCLES CYCLES Figure 16-1. Power-On Reset Recovery is below the LVI DD MC68HC908LB8 Data Sheet, Rev. 1 voltage TRIPF voltage and during the oscillator TRIPF Freescale Semiconductor ...
Page 165
... MODRST — Monitor Mode Entry Module Reset Bit 1 = Last reset caused by forced monitor mode entry POR or read of SRSR since any reset LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by low-power supply voltage 0 = POR or read of SRSR since any reset Freescale Semiconductor NOTE ...
Page 166
... High byte of index register is not stacked. 166 • • • CONDITION CODE REGISTER 1 ACCUMULATOR 2 (1) INDEX REGISTER (LOW BYTE PROGRAM COUNTER (LOW BYTE) 5 • • • $00FF DEFAULT ADDRESS ON RESET Figure 16-3. Interrupt Stacking Order MC68HC908LB8 Data Sheet, Rev. 1 UNSTACKING ORDER Freescale Semiconductor ...
Page 167
... H register or uses the indexed addressing mode, save the H register and then restore it prior to exiting the routine. See Figure 16-5 for a flowchart depicting interrupt processing. 16.3.2 Sources The sources in Table 16-1 can generate CPU interrupt requests. Freescale Semiconductor CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH ...
Page 168
... AIEN MC68HC908LB8 Data Sheet, Rev. 1 Vector (2) Address 0 $FFFE–$FFFF 1 $FFFC–$FFFD 2 $FFFA–$FFFB 3 $FFF6–$FFF7 4 $FFF4–$FFF5 5 $FFF2–$FFF3 6 $FFF1–$FFF0 7 $FFEF–$FFEE 8 $FFED–$FFEC 9 $FFE0–$FFE1 10 $FFDF-$FFDE Freescale Semiconductor ...
Page 169
... FROM RESET INTERRUPT YES I BIT SET? I BIT SET? INTERRUPT INTERRUPT INTERRUPTS FETCH NEXT INSTRUCTION INSTRUCTION INSTRUCTION 16.3.2.1 Software Interrupt (SWI) Instruction The software interrupt (SWI) instruction causes a non-maskable interrupt. Freescale Semiconductor YES BREAK ? NO NO YES IRQ ? NO YES CGM ? NO OTHER YES ? NO STACK CPU REGISTERS ...
Page 170
... CPU interrupt when the PWM reload flag (PWMF) is set. The PWMF bit is set at the beginning of every reload cycle. 16.3.2.8 High Resolution PWM (HRP) When the SHTIE bit is set, the HRP module is capable of generating a CPU interrupt on detection of a falling edge or a low level on the SHTDN pin. 170 NOTE MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 171
... Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation • CPU enable/disable timing • Modular architecture expandable to 128 interrupt sources Table 17-1 shows the internal signal names used in this section. Freescale Semiconductor MC68HC908LB8 Data Sheet, Rev. 1 171 ...
Page 172
... CPU WAIT (FROM CPU) SIMOSCEN (TO OSC) COP CLOCK BUSCLKX4 (FROM OSC) BUSCLKX2 (FROM OSC) INTERNAL CLOCKS FORCED MONITOR MODE ENTRY LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE Freescale Semiconductor ...
Page 173
... Upon exit from stop mode by an interrupt or reset, the SIM allows BUSCLKX4 to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay time out. This time out is selectable as 4096 or 32 BUSCLKX4 cycles. See Freescale Semiconductor Bit 7 6 ...
Page 174
... SIM Counter), but an external reset does not. Each of shows the relative timing. Table 17-2. PIN Bit Set Timing Number of Cycles Required to Set PIN 4163 (4096 + ( VECT H VECT L Figure 17-4. External Reset Timing MC68HC908LB8 Data Sheet, Rev. 1 17.7 SIM Registers. Freescale Semiconductor ...
Page 175
... The RST pin is driven low during the oscillator stabilization time. • The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. Freescale Semiconductor NOTE RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES Figure 17-5. Internal Reset Timing ...
Page 176
... TRIPF (RST) is held low while the SIM counter counts out 4096 + 32 BUSCLKX4 cycles. Thirty-two BUSCLKX4 176 32 CYCLES Figure 17-7. POR Recovery while the MCU is in monitor mode. The COP TST MC68HC908LB8 Data Sheet, Rev. 1 $FFFE $FFFF voltage falls to the DD Freescale Semiconductor ...
Page 177
... At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. interrupt entry timing. Figure 17-9 Freescale Semiconductor 17.6.2 Stop Mode 17.3.2 Active Resets from Internal Sources shows interrupt recovery timing. ...
Page 178
... SP – – – – Figure 17-8 Interrupt Entry Timing SP – – – – 1 [7:0] PC – 1 [15:8] OPCODE Figure 17-9. Interrupt Recovery Timing Figure 17-10. MC68HC908LB8 Data Sheet, Rev. 1 VECT H VECT L START ADDR CCR V DATA H V DATA L OPCODE OPERAND Freescale Semiconductor ...
Page 179
... YES AS MANY INTERRUPTS AS EXIST ON CHIP Freescale Semiconductor FROM RESET BREAK I BIT SET? YES INTERRUPT BIT SET? NO IRQ YES INTERRUPT? NO STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES UNSTACK CPU REGISTERS INSTRUCTION? NO EXECUTE INSTRUCTION Figure 17-10. Interrupt Processing MC68HC908LB8 Data Sheet, Rev ...
Page 180
... CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Interrupt Recognition Example NOTE NOTE (BRK)). The SIM puts the CPU into the break state by MC68HC908LB8 Data Sheet, Rev. 1 BACKGROUND ROUTINE Freescale Semiconductor ...
Page 181
... IAB WAIT ADDR IDB R/W Note: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Freescale Semiconductor show the timing for WAIT recovery. WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 17-12. Wait Mode Entry Timing MC68HC908LB8 Data Sheet, Rev. 1 ...
Page 182
... To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0. 182 $6E0B $6E0C $00FF $00FE $A6 $A6 $01 $ CYCLES CYCLES $A6 NOTE Figure 17-15 NOTE MC68HC908LB8 Data Sheet, Rev. 1 $00FD $00FC $6E RST VCT H RST VCT L shows stop mode entry timing. Freescale Semiconductor ...
Page 183
... Bit 7 Read: R Write: Reset Writing a 0 clears SBSW. Figure 17-17. Break Status Register (BSR) Freescale Semiconductor STOP ADDR + 1 PREVIOUS DATA NEXT OPCODE Figure 17-15. Stop Mode Entry Timing STOP RECOVERY PERIOD STOP + 2 STOP + 2 Table 17-3 shows the mapping of these registers. ...
Page 184
... Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR 184 PIN COP ILOP ILAD MC68HC908LB8 Data Sheet, Rev Bit 0 MODRST LVI Freescale Semiconductor ...
Page 185
... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Freescale Semiconductor ...
Page 186
... System Integration Module (SIM) 186 MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 187
... POWER V SS Notes: 1. Pin contains integrated pullup device. 2. Fault function switchable between pins PTB2 and PTB7. Figure 18-1. Block Diagram Highlighting TIM Block and Pins Freescale Semiconductor Figure 18-2 INTERNAL BUS DUAL CHANNEL PWM MODULE HIGH RESOLUTION PWM MODULE LOW-VOLTAGE INHIBIT ...
Page 188
... MS0A MS0B ELS1B ELS1A CH1F MS1A Figure 18-2. TIM Block Diagram MC68HC908LB8 Data Sheet, Rev. 1 TOF INTERRUPT LOGIC TOIE TOV0 PORT CH0MAX TCH0 LOGIC INTERRUPT LOGIC CH0IE TOV1 PORT CH1MAX TCH1 LOGIC (Not available on port pin) INTERRUPT LOGIC CH1IE Freescale Semiconductor ...
Page 189
... Read: Timer Channel 0 $0027 Register Low (T1CH0L) Write: See page 201. Reset: Read: Timer Channel 1 Status and $0028 Control Register (T1SC1) Write: See page 198. Reset: Figure 18-3. TIM I/O Register Summary (Sheet Freescale Semiconductor Bit TOF 0 TOIE TSTOP 0 TRST Bit 15 ...
Page 190
... The interrupt routine has until the end of the counter overflow period to write the new value. 190 Bit Bit Indeterminate after reset Bit Indeterminate after reset = Unimplemented MC68HC908LB8 Data Sheet, Rev Bit Bit Bit 0 18.3.3 Freescale Semiconductor ...
Page 191
... PWM pulse is logic 1. Program the TIM to set the pin if the state of the PWM pulse is logic 0. OVERFLOW PULSE WIDTH TCHx Figure 18-4. PWM Period and Pulse Width Freescale Semiconductor NOTE OVERFLOW PERIOD OUTPUT OUTPUT COMPARE COMPARE MC68HC908LB8 Data Sheet, Rev ...
Page 192
... TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. 192 18.8.1 TIM Status and Control NOTE MC68HC908LB8 Data Sheet, Rev. 1 Register. 18.3.4 Pulse Width Freescale Semiconductor ...
Page 193
... Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. See 18.8.4 TIM Channel Status and Control 18.4 Interrupts The following TIM sources can generate interrupt requests: Freescale Semiconductor NOTE Table 18-2. NOTE Registers ...
Page 194
... Port B shares its pins with the TIM. Only TCH0 is available on a port pin programmable independently as an input capture pin or an output compare pin. TCH0 can be configured as buffered output compare or buffered PWM pins. 194 17.7.3 Break Flag Control Register. MC68HC908LB8 Data Sheet, Rev. 1 Freescale Semiconductor ...
Page 195
... TIM overflow interrupts disabled TSTOP — TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit TIM counter stopped 0 = TIM counter active Freescale Semiconductor ...
Page 196
... TIM Clock Source Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Not available MC68HC908LB8 Data Sheet, Rev Bit Bit Freescale Semiconductor ...
Page 197
... Flags input captures and output compares • Enables input capture and output compare interrupts • Selects input capture, output compare, or PWM operation • Selects high, low, or toggling output on output compare • Selects rising edge, falling edge, or any edge as the active input capture trigger Freescale Semiconductor ...
Page 198
... Reset clears the CHxF bit. Writing CHxF has no effect Input capture or output compare on channel input capture or output compare on channel x 198 CH0IE MS0B MS0A ELS0B CH1IE MS1A ELS1B MC68HC908LB8 Data Sheet, Rev Bit 0 ELS0A TOV0 CH0MAX Bit 0 ELS1A TOV1 CH1MAX Freescale Semiconductor ...
Page 199
... When ELSxB and ELSxA are both clear, channel x is not connected to port D, and pin PTDx/TCHx is available as a general-purpose I/O pin. the ELSxB and ELSxA bits. Before enabling a TIM channel register for input capture operation, make sure that the PTD/TCHx pin is stable for at least two bus clocks. Freescale Semiconductor Table 18-2. NOTE Table 18-2 shows how ELSxB and ELSxA work ...
Page 200
... Clear output on compare or buffered PWM 11 Set output on compare NOTE shows, the CHxMAX bit takes effect in the cycle after it is set OVERFLOW OVERFLOW OUTPUT OUTPUT COMPARE COMPARE Figure 18-12. CHxMAX Latency MC68HC908LB8 Data Sheet, Rev. 1 Configuration OVERFLOW OVERFLOW OUTPUT COMPARE Freescale Semiconductor ...