MCHC908GR8AVFAE Freescale Semiconductor, MCHC908GR8AVFAE Datasheet
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MC68HC908GR8A MC68HC908GR4A Data Sheet M68HC08 Microcontrollers MC68HC908GR8A Rev. 5 04/2007 freescale.com ...
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...
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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005, 2007. All rights reserved. ...
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... MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Description max to 8.5 V TST max to 8.5 V TST Page Number(s) N/A Throughout Throughout Throughout Throughout 40— 75, 76 79 118, 123, 126 134 136 139 157—173 195 213 215—230 215 221 233 234 247 247 248 Freescale Semiconductor ...
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... Chapter 5 Configuration Register (CONFIG) CGMXCLK and corrected what set and cleared indicate for bit April, 5 CONFIG1_COPRS 2007 10.6.2 Stop Mode MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Description — Replaced COPCLK with — Replaced COPCLK with CGMXCLK Page Number(s) 248 229 ...
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... Revision History MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Freescale Semiconductor ...
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... Chapter 15 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Chapter 16 Timebase Module (TBM 195 Chapter 17 Timer Interface Module (TIM1 and TIM2 199 Chapter 18 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Chapter 19 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Chapter 20 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 249 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 7 ...
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... List of Chapters MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Freescale Semiconductor ...
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... FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.6.4 FLASH Mass Erase Operation 2.6.5 FLASH Program/Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.6.6 FLASH Block Protection 2.6.7 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.6.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 1 General Description and and DDA SSA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CGMXFC /V ...
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... CGM Base Clock Output (CGMOUT 4.4.10 CGM CPU Interrupt (CGMINT MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Chapter 3 Analog-to-Digital Converter (ADC) )/ADC Voltage Reference Low Pin (V SSAD )/ADC Voltage Reference High Pin (V DDAD ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Chapter 4 Clock Generator Module (CGM DDA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SSA ) . . . . . . . . . . . 51 REFL ) . . . . . . . . . . . 51 REFH Freescale Semiconductor ...
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... Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.2 Features MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 5 Configuration Register (CONFIG) Chapter 6 Chapter 7 Central Processor Unit (CPU) 11 ...
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... Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.2.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.3 Break Module (BRK 106 10.3.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 10.3.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Chapter 8 External Interrupt (IRQ) Chapter 9 Keyboard Interrupt Module (KBI) Chapter 10 Low-Power Modes Freescale Semiconductor ...
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... Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.3.4 LVI Trip Selection 113 11.4 LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 11 Low-Voltage Inhibit (LVI) 13 ...
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... Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.4.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.4.3.7 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.4.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Chapter 12 Input/Output (I/O) Ports Chapter 13 Freescale Semiconductor ...
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... Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 14.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.7.1 SIM Break Status Register 171 14.7.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 14.7.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 14 System Integration Module (SIM) 15 ...
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... Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.6 Timebase Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Timer Interface Module (TIM1 and TIM2) 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 17.2 Features 201 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Chapter 15 Chapter 16 Timebase Module (TBM) Chapter 17 Freescale Semiconductor ...
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... Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 18.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 18.3.1.3 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 18.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 18.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 18.3.1.6 Baud Rate 226 18.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 18.3.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 18 Development Support 17 ...
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... CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 19.16 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 19.17 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Ordering Information and Mechanical Specifications 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 20.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 20.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Chapter 19 Electrical Specifications Chapter 20 Freescale Semiconductor ...
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... Low-power design; fully static with stop and wait modes • Standard low-power modes of operation: – Wait mode – Stop mode 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor (1) 19 ...
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... Memory-to-memory data transfers Fast 8 × 8 multiply instruction • • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Freescale Semiconductor ...
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... DDA V SSA 1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor INTERNAL BUS PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT ...
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... V PTD0/ PTD1/MISO 20 9 PTB3/AD3 PTD2/MOSI 10 19 PTB2/AD2 PTD3/SPSCK 18 11 PTB1/AD1 PTB0/AD0 PTD6/T2CH0 DD PTD4/T1CH0 15 14 PTD5/T1CH1 Figure 1-3 illustrate the pin assignments PTA2/KBD2 24 23 PTA1/KBD1 22 PTA0/KBD0 SSAD REFL DDAD REFH 19 PTB5/AD5 18 PTB4/AD4 PTB3/AD3 17 SSA DDA /V SSAD REFL /V DDAD REFH Freescale Semiconductor ...
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... It is driven low when any internal reset source is asserted. This pin contains an internal pullup resistor. See Chapter 14 System Integration Module (SIM). 1.5.4 External Interrupt Pin (IRQ) IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor. See Chapter 8 External Interrupt (IRQ). MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor and MCU V ...
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... Ports. Chapter 17 Timer Interface Module (TIM1 and Module, and Chapter 12 Input/Output (I/O) Chapter 4 Clock Generator Module Chapter 4 Clock Generator Module and SSAD REFL and V REFH /V pin should be connected SSAD REFL (ADC). and Chapter 9 and Chapter 3 Analog-to-Digital TIM2), Ports. Freescale Semiconductor REFL . DD ...
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... Any unused inputs and I/O ports should be tied to an appropriate logic level (either require termination, termination is recommended to reduce the possibility of static damage. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 13 Serial Communications Interface (SCI) Ports. NOTE ). Although the I/O ports of the MC68HC908GR8A do not Pin Functions 25 ...
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... General Description MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Freescale Semiconductor ...
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... BRKSCR • $FE0C; LVI status register, LVISR • $FF7E; FLASH block protect register, FLBPR Data registers are shown in Figure MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 2-2. Table 2 list of vector locations. Figure 2-1, includes: (Figure 2-1) ...
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... SIM BREAK FLAG CONTROL REGISTER (SBFCR) INTERRUPT STATUS REGISTER 1 (INT1) INTERRUPT STATUS REGISTER 2 (INT2) INTERRUPT STATUS REGISTER 3 (INT3) Reserved for FLASH Test Control Register (FLTCR) Figure 2-1. Memory Map RAM MC68HC908GR4A RESERVED 3584 BYTES MC68HC908GR4A FLASH MEMORY 4096 BYTES Freescale Semiconductor ...
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... Figure 2-1. Memory Map (Continued) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor FLASH CONTROL REGISTER (FLCR) BREAK ADDRESS REGISTER HIGH (BRKH) BREAK ADDRESS REGISTER LOW (BRKL) BREAK STATUS AND CONTROL REGISTER (BRKSCR) LVI STATUS REGISTER (LVISR) RESERVED ↓ ...
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... Unaffected by reset Unimplemented R = Reserved Bit 0 PTA3 PTA2 PTA1 PTA0 PTB3 PTB2 PTB1 PTB0 0 0 PTC1 PTC0 PTD3 PTD2 PTD1 PTD0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 PTE1 PTE0 DDRE1 DDRE0 Unaffected Freescale Semiconductor ...
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... See page 149. Reset: Read: SCI Status Register 1 $0016 (SCS1) Write: See page 151. Reset: Read: SCI Status Register 2 $0017 (SCS2) Write: See page 153. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Bit ...
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... TOF 0 TOIE TSTOP 0 TRST Bit Unimplemented R = Reserved Bit SCR2 SCR1 SCR0 KEYF 0 IMASKK MODEK ACKK KBIE3 KBIE2 KBIE1 KBIE0 TBIE TBON R TACK IRQF 0 IMASK MODE ACK OSC- SCIBDSRC STOPENB LVI5OR3 SSREC STOP COPD (Note PS2 PS1 PS0 Bit Unaffected Freescale Semiconductor ...
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... Timer 2 Status and Control $002B Register (T2SC) Write: See page 211. Reset: Read: Timer 2 Counter $002C Register High (T2CNTH) Write: See page 210. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Bit Bit Bit 15 14 ...
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... Indeterminate after reset PLLF PLLIE PLLON BCS LOCK 0 AUTO ACQ MUL7 MUL6 MUL5 MUL4 Unimplemented R = Reserved Bit Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit Bit PRE1 PRE0 VPR1 VPR0 MUL11 MUL10 MUL9 MUL8 MUL3 MUL2 MUL1 MUL0 Unaffected Freescale Semiconductor ...
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... SIM Break Flag Control $FE03 Register (SBFCR) Write: See page 220. Reset: Read: Interrupt Status Register 1 $FE04 (INT1) Write: See page 167. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Bit VRS7 VRS6 VRS5 VRS4 ...
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... BPR7 BPR6 BPR5 BPR4 Unaffected by reset Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented R = Reserved Bit 0 IF10 IF9 IF8 IF7 IF16 IF15 HVEN MASS ERASE PGM Bit Bit BPR3 BPR2 BPR1 BPR0 U = Unaffected Freescale Semiconductor ...
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... Vector Priority Lowest Highest MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor . Table 2-1. Vector Addresses Vector Address $FFDC Timebase Vector (High) IF16 $FFDD Timebase Vector (Low) $FFDE ADC Conversion Complete Vector (High) IF15 $FFDF ADC Conversion Complete Vector (Low) $FFE0 ...
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... A security feature prevents viewing of the FLASH contents security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev NOTE NOTE NOTE NOTE (1) Freescale Semiconductor ...
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... PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal set the same time Program operation selected 0 = Program operation unselected MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ...
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... After a time, t RCV 1. When in monitor mode, with security sequence failed (see of any FLASH address. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev NOTE (1) within the FLASH memory address range. NOTE 18.3.2 Security), write to the FLASH block protect register instead Freescale Semiconductor ...
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... Care must be taken within the FLASH array memory space such as the COP control register (COPCTL) at $FFFF highly recommended that interrupts be disabled during program/ erase operations. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE (Figure 2-4 NOTE NOTE NOTE ...
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... Therefore, if this page is not protected by FLBPR the register is erased by either a page or mass erase operation. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev NOTE maximum or t maximum. t PROG HV x 32) ≤ NVH PGS PROG Characteristics. NOTE CAUTION NOTE NOTE is defined as the HV maximum HV TST Freescale Semiconductor on the ...
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... PROG This row program algorithm assumes the row programmed are initially erased. Figure 2-4. FLASH Programming Flowchart MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS ...
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... FFFF $FF40 (1111 1111 0100 0000) — $FFFF FLBPR and vectors are protected $FF80 (1111 1111 1000 0000) — FFFF Vectors are protected The entire FLASH memory is not protected Bit 0 BPR2 BPR1 BPR0 Freescale Semiconductor ...
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... FLASH, otherwise the operation will discontinue, and the FLASH will be on standby mode Standby mode is the power saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH minimum. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE FLASH Memory (FLASH) 45 ...
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... Memory MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Freescale Semiconductor ...
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... I/O logic and can be used as general-purpose I/O. Writes to the port register or data direction register (DDR) will not have any affect on the port pin that is selected by the ADC. Read of a port pin in use by the ADC will return a 0. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ). ADIN 47 ...
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... MONITOR MODULE MEMORY MAP MODULE CONFIGURATION REGISTER 1 MODULE CONFIGURATION REGISTER 2 MODULE PTA3/KBD3– (1) PTA0/KBD0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1), (2) PTC1 (1), (2) PTC0 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
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... V DDA REFH Connect the V DDA connect the V SSA V pin should be routed carefully for maximum noise immunity. DDA MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor DDRBx PTBx ADC DATA REGISTER ADC VOLTAGE IN (V ADIN V ADC V ...
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... The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev ADC cycles ADC frequency Freescale Semiconductor ...
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... In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion. COCO will stay set until cleared by a read of the ADC data register. Reset clears this bit. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor )/ADC Voltage Reference Low Pin (V SSAD ...
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... NOTE Table 3-1. NOTE Table 3-1. Mux Channel Select ADCH2 ADCH1 ADCH0 ↓ ↓ ↓ Table 3-1. Care should be taken Table 3-1, are used to verify (1) Input Select PTB0/KBD0 PTB1/AD1 PTB1/AD2 PTB2/AD3 PTB4/AD4 PTB5/AD5 Reserved V REFH V REFL ADC power off Freescale Semiconductor ...
Page 53
... ADICLK selects either the bus clock or the oscillator output clock (CGMXCLK) as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source Internal bus clock 0 = Oscillator output clock (CGMXCLK) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 54
... The ADC requires a clock rate of approximately 1 MHz for correct operation. If the selected clock source is not fast enough, the ADC will generate incorrect conversions. See f ADIC MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev bus frequency CGMXCLK = ADIV[2:0] 19.12 ADC Characteristics. ≅ 1 MHz Freescale Semiconductor ...
Page 55
... Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK. Figure 4-1 shows the structure of the CGM. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 55 ...
Page 56
... VRS7–VRS0 VOLTAGE LOOP CONTROLLED FILTER OSCILLATOR PLL ANALOG AUTOMATIC INTERRUPT MODE CONTROL CONTROL AUTO ACQ PLLIE PLLF PRE1–PRE0 FREQUENCY DIVIDER Figure 4-1. CGM Block Diagram CGMXCLK (TO: SIM, TIM, ADC) CLOCK CGMOUT SELECT ÷ 2 CIRCUIT (TO SIM) CGMVCLK PLLIREQ (TO SIM) Freescale Semiconductor ...
Page 57
... The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the reference clock, CGMRCLK. Therefore, the speed of the lock detector is directly proportional to the reference MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor , (38.4 kHz) times a linear factor, L, and a power-of-two factor Modes. The value of the external capacitor and the Functional Description ...
Page 58
... MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev 4.5.2 PLL Bandwidth Control 4.3.8 Base Clock Selector Circuit.) The PLL is automatically in Register read-only indicator of the mode of Modes.) 4.8 Acquisition/Lock Time Specifications 4.8 Acquisition/Lock Time Specifications Register.) Register.) 4.5.2 PLL 4.3.8 Base Clock Selector Circuit.) for for Freescale Semiconductor ...
Page 59
... R with RCLK practical choices of f RCLK R = round R MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Specifications), after turning on the PLL by setting PLLON in the PLL , after entering tracking mode before selecting the PLL as the AL NOTE . BUSDES × ...
Page 60
... VCLK 8MHz ≤ f < 16MHz VCLK 16MHz ≤ f < 32MHz VCLK = 38.4 kHz NOM ⎛ ⎞ f VCLK ⎜ ⎟ round -------------------------- ⎝ E ⎠ × NOM E ( × VRS NOM E × NOM ≤ -------------------------- f f – VRS VCLK and f . VCLK BUS The VRS Freescale Semiconductor ...
Page 61
... BUS 2.0 4.0 8.0 2.0 4.0 8.0 2.4576 4.9152 7.3728 2.0 4.0 8.0 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor VCLK NOTE Table 4-1. Numeric Example PCTL (MHz) RCLK 4.0 ...
Page 62
... Routing should be done with great care to minimize signal cross talk and noise. See 19.15 Clock Generation Module Characteristics MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev 4.3.6 Programming the PLL Circuit.) for capacitor and resistor values. does not account for three possible Figure Freescale Semiconductor 4-2. ...
Page 63
... Figure To prevent noise problems, the filter network should be placed as close to the CGMXFC pin as possible, with minimum routing distances and no routing of other signals across the network. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor CGMXCLK CGMXFC OSC2 R F1 ...
Page 64
... CGMINT is the interrupt signal generated by the PLL lock detector. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev DDA NOTE ) SSA NOTE Figure 4-2 shows only the logical relation of CGMXCLK to OSC1 pin to the same voltage DDA pin to the same voltage SSA ) and comes XCLK Freescale Semiconductor ...
Page 65
... When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only. 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only. Figure 4-3. CGM I/O Register Summary MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Register.) High.) Low.) Register.) Register ...
Page 66
... PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev PLLF PLLON BCS PRE1 NOTE NOTE 2 1 Bit 0 PRE0 VPR1 VPR0 4.3.8 Base Clock 4.3.8 Base Clock Freescale Semiconductor ...
Page 67
... In manual operation, forces the PLL into acquisition or tracking mode Address: $0037 Bit 7 Read: AUTO Write: Reset Unimplemented Figure 4-5. PLL Bandwidth Control Register (PBWC) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Circuit.) PLL.) PRE1 and PRE0 cannot be written when the PLLON bit is set 4.3.6 Programming the PLL, and E ...
Page 68
... PLL is on (PLLON = 1). PMSH[7:4] — Unimplemented Bits These bits have no function and always read as 0s. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev MUL11 4.3.3 PLL Circuits and 4.3.6 Programming the NOTE 2 1 Bit 0 MUL10 MUL9 MUL8 PLL.) A value of $0000 in Freescale Semiconductor ...
Page 69
... VRS7–VRS0 — VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with E (see 4.3.3 PLL Circuits, 4.3.6 Programming the hardware center-of-range frequency, f PCTL is set. (See 4.3.7 Special Programming MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor MUL6 MUL5 MUL4 MUL3 1 ...
Page 70
... If the application is not frequency MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Exceptions.). Reset initializes the register to NOTE RDS3 4.3.6 Programming the PLL.) RDS7–RDS0 cannot be written when the 4.3.7 Special Programming NOTE 4.3.8 Base 2 1 Bit 0 RDS2 RDS1 RDS0 Exceptions.) Reset Freescale Semiconductor ...
Page 71
... The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE 14.7.1 SIM Break Status Register.) ...
Page 72
... PLL through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev 4.3.3 PLL Circuits, Register.) 4.8.3 Choosing a . The power supply potential alters the DDA RDV and the XCLK 4.3.6 Programming the PLL, and Filter.) Freescale Semiconductor . ...
Page 73
... SSA Table 4-4. Example Filter Component Values f RCLK 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Time, the external filter network is critical to the Figure 4-10(A). Refer to Table 4-4 ( Figure 4-10. PLL Filter 8.2 nF 820 pF 4 ...
Page 74
... Clock Generator Module (CGM) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Freescale Semiconductor ...
Page 75
... FLASH memory but are special registers containing one-time writable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Address: $001E Bit 7 6 Read Write: Reset Unimplemented Figure 5-1. Configuration Register 2 (CONFIG2) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE Figure 5-1 and Figure ...
Page 76
... See note (CGM). This function is used to keep the timebase running while Chapter 16 Timebase Module Chapter 11 Low-Voltage Inhibit 2 1 Bit 0 SSREC STOP COPD (TBM). When clear, the oscillator will Chapter 13 Serial Communications Chapter 6 Computer Operating Chapter 11 Low-Voltage Inhibit (LVI). Freescale Semiconductor (LVI). ...
Page 77
... STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. See 1 = COP module disabled 0 = COP module enabled MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 11 Low-Voltage Inhibit NOTE NOTE Chapter 6 Computer Operating Properly (COP) Functional Description ...
Page 78
... Configuration Register (CONFIG) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Freescale Semiconductor ...
Page 79
... COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SELECT (COPRS FROM CONFIG1) 1. See Chapter 14 System Integration Module (SIM) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor SIM MODULE 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER for more details ...
Page 80
... The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up. 6.3.5 Internal Reset An internal reset clears the COP prescaler and the COP counter. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev NOTE . During the break state, TST NOTE Figure 6-1. 6.4 COP Freescale Semiconductor ...
Page 81
... Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 82
... STOP instruction. When the STOP bit in the configuration register has the STOP instruction disabled, execution of a STOP instruction results in an illegal opcode reset. 6.8 COP Module During Break Mode The COP is disabled during a break interrupt when V MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev present on the RST pin. TST Freescale Semiconductor ...
Page 83
... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 7.3 CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 83 ...
Page 84
... STACK POINTER (SP) 0 PROGRAM COUNTER (PC CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers Unaffected by reset Figure 7-2. Accumulator ( Figure 7-3. Index Register (H: Bit 0 Bit Freescale Semiconductor ...
Page 85
... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 86
... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev NOTE 2 1 Bit Freescale Semiconductor ...
Page 87
... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Arithmetic/Logic Unit (ALU) 87 ...
Page 88
... EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 – – IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 – – IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 Freescale Semiconductor ...
Page 89
... CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Description ← (PC rel ? ( – – – – – – REL PC ← (PC rel ? IRQ = 1 – – – – – – REL PC ← (PC rel ? IRQ = 0 – ...
Page 90
... DIR INH 4A 1 INH 5A 1 – – – IX1 SP1 9E6A ff 5 INH 52 7 IMM DIR EXT IX2 – IX1 SP1 9EE8 ff 4 SP2 9ED8 DIR INH 4C 1 INH 5C 1 – – – IX1 SP1 9E6C ff 5 Freescale Semiconductor ...
Page 91
... ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Effect on CCR Description ← Jump Address – – – – – – PC ← (PC Push (PCL); SP ← (SP) – 1 – ...
Page 92
... IX2 IX1 SP1 9EE2 ff 4 SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF IMM DIR EXT IX2 IX1 SP1 9EE0 ff 4 SP2 9ED0 Freescale Semiconductor ...
Page 93
... Memory location N Negative bit 7.8 Opcode Map See Table 7-2. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Description ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) – – 1 – – – INH SP ← (SP) – 1; Push (CCR) SP ← ...
Page 94
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
Page 95
... The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin. When an interrupt pin is edge-triggered only (MODE = 0), the interrupt remains set until a vector fetch, software clear, or reset occurs. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 95 ...
Page 96
... V DD CLR IMASK MODE Figure 8-1. IRQ Module Block Diagram NOTE Bit Unimplemented Figure 8-2. IRQ I/O Register Summary TO CPU FOR BIL/BIH INSTRUCTIONS IRQF IRQ SYNCHRONIZER INTERRUPT REQUEST TO MODE HIGH SELECT VOLTAGE DETECT LOGIC IRQF 0 IMASK ACK Freescale Semiconductor Bit 0 MODE 0 ...
Page 97
... To protect CPU interrupt flags during the break state, write the BCFE bit. With BCFE at 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ interrupt flags. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE Support. IRQ Pin ...
Page 98
... This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev IRQF Bit 0 0 IMASK MODE ACK Freescale Semiconductor ...
Page 99
... If the keyboard interrupt is falling edge- and low-level sensitive, an interrupt request is present as long as any keyboard interrupt pin is low and the pin is keyboard interrupt enabled. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 99 ...
Page 100
... MONITOR MODULE MEMORY MAP MODULE CONFIGURATION REGISTER 1 MODULE CONFIGURATION REGISTER 2 MODULE PTA3/KBD3– (1) PTA0/KBD0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1), (2) PTC1 (1), (2) PTC0 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
Page 101
... Return of all enabled keyboard interrupt pins to a high level — As long as any enabled keyboard interrupt pin is low, the keyboard interrupt remains set. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ACKK V DD CLR ...
Page 102
... Wait Mode The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 102 NOTE Freescale Semiconductor ...
Page 103
... This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit Keyboard interrupt pending keyboard interrupt pending ACKK — Keyboard Acknowledge Bit Writing this write-only bit clears the keyboard interrupt request. ACKK always reads as 0. Reset clears ACKK. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 9.7.1 Keyboard Status and Control ...
Page 104
... Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register PTAx pin enabled as keyboard interrupt pin 0 = PTAx pin not enabled as keyboard interrupt pin MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 104 KBIE3 Bit 0 KBIE2 KBIE1 KBIE0 Freescale Semiconductor ...
Page 105
... The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 5 Chapter 5 Configuration Register 105 ...
Page 106
... CGM (oscillator and phase-locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT). If the OSCSTOPENB bit in the CONFIG2 register is set, then the phase locked loop is shut off, but the oscillator will continue to operate in stop mode. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 106 Freescale Semiconductor ...
Page 107
... The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Computer Operating Properly Module (COP) 107 ...
Page 108
... The SPI module is inactive in stop mode. The STOP instruction does not affect SPI register states. SPI operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is aborted, and the SPI is reset. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 108 Freescale Semiconductor ...
Page 109
... Low-voltage inhibit (LVI) reset — A power supply voltage below the V and loads the program counter with the contents of locations $FFFE and $FFFF. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Timer Interface Module (TIM1 and TIM2) voltage resets the MCU TRIPF ...
Page 110
... Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32 CGMXCLK cycles. Use the full stop recovery time (SSREC = 0) in applications that use an external crystal unless the OSCSTOPENB bit is set. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 110 NOTE Freescale Semiconductor ...
Page 111
... V which will re-trigger the power-on reset and reset the trip point to 3-V operation. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor voltage falls below the LVI trip falling voltage voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI ...
Page 112
... V DD TRIPF to remain above the V level, enabling LVI resets allows the LVI TRIPF falls below the V level. In the configuration register, the DD TRIPF , which causes the MCU TRIPR LVISTOP FROM CONFIG1 LVI RESET level, software can monitor V DD Freescale Semiconductor Bit polling ...
Page 113
... The LVI module does not generate interrupt requests. 11.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor fall below V ), the LVI will maintain a reset condition until DD TRIPF ...
Page 114
... If enabled in stop mode (LVISTOP bit in the configuration register is set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 114 Freescale Semiconductor ...
Page 115
... Write: See page 122. Reset: Read: Port D Data Register $0003 (PTD) Write: See page 124. Reset: Read: Data Direction Register A $0004 (DDRA) Write: See page 118. Reset: MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE Bit PTB5 PTD6 PTD5 0 0 ...
Page 116
... Bit DDRB5 DDRB4 DDRD6 DDRD5 DDRD4 Unaffected by reset PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0 Unimplemented Bit 0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 PTE1 PTE0 0 0 DDRE1 DDRE0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 PTCPUE1 PTCPUE0 Freescale Semiconductor ...
Page 117
... The port A data register (PTA) contains a data latch for each of the four port A pins. Address: $0000 Bit 7 Read: 0 Write: Reset: Alternative Function: = Unimplemented MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor DDR Module Control DDRA0 KBIE0 DDRA1 KBIE1 KBD DDRA2 KBIE2 DDRA3 KBIE3 ...
Page 118
... WRITE DDRA ($0004) WRITE PTA ($0000) READ PTA ($0000) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 118 Chapter 9 Keyboard Interrupt Module (KBI DDRA3 NOTE DDRAx RESET PTAx Figure 12-4. Port A I/O Circuit 2 1 Bit 0 DDRA2 DDRA1 DDRA0 PTAPUEx INTERNAL PULLUP DEVICE PTAx Freescale Semiconductor ...
Page 119
... These writeable bits are software programmable to enable pullup devices on an input port bit Corresponding port A pin configured to have internal pullup 0 = Corresponding port A pin has internal pullup disconnected MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Table 12-2 summarizes the operation of the port A pins. Table 12-2. Port A Pin Functions ...
Page 120
... Figure 12-7. Data Direction Register B (DDRB) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 120 PTB5 PTB4 PTB3 Unaffected by reset AD5 AD4 AD3 Figure 12-6. Port B Data Register (PTB) NOTE DDRB5 DDRB4 DDRB3 Bit 0 PTB2 PTB1 PTB0 AD2 AD1 AD0 2 1 Bit 0 DDRB2 DDRB1 DDRB0 Freescale Semiconductor ...
Page 121
... X Output Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE DDRBx RESET PTBx Figure 12-8. Port B I/O Circuit Table 12-3 summarizes the operation of the port B pins. ...
Page 122
... PTC1–PTC0 are not connected. Set DDRC1 and DDRC0 configure PTC1–PTC0 as outputs. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 122 Unaffected by reset Figure 12-9. Port C Data Register (PTC) NOTE NOTE 2 1 Bit 0 0 PTC1 PTC0 2 1 Bit 0 0 DDRC1 DDRC0 Freescale Semiconductor ...
Page 123
... I/O pin pulled internal pullup device Writing affects data register, but does not affect input. 4. Hi-Z = High impedance MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor DDRCx RESET PTCx Figure 12-11. Port C I/O Circuit Table 12-4 summarizes the operation of the port C pins. ...
Page 124
... I/O pin. See MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 124 PTD6 PTD5 PTD4 PTD3 Unaffected by reset T2CH0 T1CH1 T1CH0 SPSCK Chapter 17 Timer Interface Module (TIM1 and 2 1 Bit 0 0 PTCPUE1 PTCPUE0 Bit 0 PTD2 PTD1 PTD0 MOSI MISO SS TIM2). Freescale Semiconductor ...
Page 125
... Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 17 Timer Interface Module (TIM1 and Table 12-5. 6 ...
Page 126
... Table 12-5. Port D Pin Functions Accesses to DDRD I/O Pin Mode Read/Write (2) Input, V DDRD6–DDRD0 DD (4) DDRD6–DDRD0 Input, Hi-Z Output DDRD6–DDRD0 V DD PTDPUEx INTERNAL PULLUP DEVICE PTDx Accesses to PTD Read Write Pin PTD6–PTD0 Pin PTD6–PTD0 PTD6–PTD0 PTD6–PTD0 Freescale Semiconductor (3) (3) ...
Page 127
... Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the ESCI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. See MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 128
... E I/O logic. READ DDRE ($000C) WRITE DDRE ($000C) WRITE PTE ($0008) READ PTE ($0008) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 128 Module. Module NOTE DDREx RESET PTEx Figure 12-19. Port E I/O Circuit 2 1 Bit 0 0 DDRE1 DDRE0 PTEx Freescale Semiconductor ...
Page 129
... X Output Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Table 12-6 summarizes the operation of the port E pins. Table 12-6. Port E Pin Functions Accesses to DDRE Read/Write (2) DDRE1– ...
Page 130
... Input/Output (I/O) Ports MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 130 Freescale Semiconductor ...
Page 131
... Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection • Mask option register bit, SCIBDSRC, to allow selection of baud rate clock source MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 131 ...
Page 132
... MONITOR MODULE MEMORY MAP MODULE CONFIGURATION REGISTER 1 MODULE CONFIGURATION REGISTER 2 MODULE PTA3/KBD3– (1) PTA0/KBD0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1), (2) PTC1 (1), (2) PTC0 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
Page 133
... The SCI uses the standard non-return-to-zero mark/space data format illustrated in START BIT 0 BIT 1 BIT START BIT BIT 0 BIT 1 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Table 13-1 Table 13-1. Pin Name Conventions Generic Pin Names: RxD Full Pin Names: PTE1/RxD 8-BIT DATA FORMAT BIT M IN SCC1 CLEAR BIT 2 ...
Page 134
... FLAG CONTROL CONTROL BKF RPF PRE- BAUD DIVIDER DATA SELECTION ÷16 Figure 13-3. SCI Module Block Diagram SCI DATA REGISTER TRANSMIT SHIFT REGISTER TXINV R8 T8 ORIE NEIE FEIE PEIE LOOPS ENSCI TRANSMIT CONTROL M WAKE ILTY PEN PTY CONTROL Freescale Semiconductor PTE0/TxD ...
Page 135
... The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8). MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Bit ...
Page 136
... MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 136 INTERNAL BUS BAUD ÷ 16 SCI DATA REGISTER DIVIDER SHIFT REGISTER TXINV M PEN PARITY GENERATION PTY T8 SCTE SCTE SCTIE SCTIE TC TC TCIE TCIE Figure 13-5. SCI Transmitter 11-BIT TRANSMIT PTE0/TxD TRANSMITTER CONTROL LOGIC SBK LOOPS ENSCI TE Freescale Semiconductor ...
Page 137
... Clears the SCI data register (SCDR) • Clears the R8 bit in SCC3 • Sets the break flag bit (BKF) in SCS2 • May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Functional Description 137 ...
Page 138
... SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 138 NOTE Freescale Semiconductor ...
Page 139
... => SCICLK = CGMXCLK => SCICLK = BUS CLOCK BKF RPF WAKE ILTY PEN ERROR CPU PTY INTERRUPT REQUEST Figure 13-6. SCI Receiver Block Diagram MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor INTERNAL BUS SCR2 SCR1 SCR0 PRE- BAUD ÷ 16 DIVIDER DATA PTE1/RxD RECOVERY ...
Page 140
... START BIT START BIT START BIT QUALIFICATION VERIFICATION SAMPLING Figure 13-7. Receiver Data Sampling Table 13-2. Start Bit Verification Start Bit Samples Verification 000 Yes 001 Yes 010 Yes 011 No 100 Yes 101 No 110 No 111 No LSB DATA Noise Flag Freescale Semiconductor ...
Page 141
... FE, in SCS1. A break character also sets the FE bit because a break character has no stop bit. The FE bit is set at the same time that the SCRF bit is set. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Table 13-3. Data Bit Recovery Data Bit ...
Page 142
... RT cycles at the point when MSB STOP DATA SAMPLES Figure 13-8. Slow Data 154 147 – × 100 = 4.54% ------------------------- - 154 Figure 13-8, the receiver counts 170 RT cycles at the point when 170 163 – × 100 = 4.12% ------------------------- - 170 Freescale Semiconductor ...
Page 143
... If they are not the same, software can set the RWU bit and put the receiver back into the standby state. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor STOP IDLE OR NEXT CHARACTER ...
Page 144
... CPU. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode. If SCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 144 NOTE Freescale Semiconductor ...
Page 145
... E. When the SCI is enabled, the PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data direction register E (DDRE). MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor for information on exiting wait mode. for information on exiting stop mode. SCI During Break Module Interrupts ...
Page 146
... This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit Transmitter output inverted 0 = Transmitter output not inverted Setting the TXINV bit inverts all transmitted values, including idle, break, start, and stop bits. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 146 ENSCI TXINV M WAKE NOTE 2 1 Bit 0 ILTY PEN PTY Freescale Semiconductor ...
Page 147
... Changing the PTY bit in the middle of a transmission or reception can generate a parity error. Control Bits M PEN and PTY MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Table 13-5. Figure NOTE Table 13-5. Character Format Selection Character Format Start Data Parity Bits Bits 1 8 None 1 9 None 1 ...
Page 148
... PTE0/TxD returns to the idle condition (1). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit Transmitter enabled 0 = Transmitter disabled MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 148 TCIE SCRIE ILIE Bit 0 RE RWU SBK Freescale Semiconductor ...
Page 149
... Receiver overrun interrupts – Noise error interrupts – Framing error interrupts • Parity error interrupts Address: $0015 Bit 7 Read: R8 Write: Reset Unimplemented Figure 13-12. SCI Control Register 3 (SCC3) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE NOTE NOTE ORIE Reserved ...
Page 150
... Transfer of SCDR data to transmit shift register complete • Transmission complete • Transfer of receive shift register data to SCDR complete • Receiver input idle • Receiver overrun • Noisy data • Framing error • Parity error MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 150 Freescale Semiconductor ...
Page 151
... ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit Receive shift register full and SCRF = receiver overrun MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 152
... BYTE 3 READ SCS1 SCRF = READ SCDR BYTE 1 BYTE 2 DELAYED FLAG CLEARING SEQUENCE BYTE 2 BYTE 3 READ SCS1 SCRF = READ SCDR BYTE 1 Figure 13-14. Flag Clearing Sequence BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 Freescale Semiconductor ...
Page 153
... Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress Reception in progress reception in progress MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 154
... SCP1 and SCP0 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 154 Unaffected by reset Figure 13-16. SCI Data Register (SCDR) NOTE SCP1 SCP0 Table 13-6. SCI Baud Rate Prescaling Prescaler Divisor (PD Bit Bit 0 SCR2 SCR1 SCR0 Reserved Table 13-6. Reset clears SCP1 Freescale Semiconductor ...
Page 155
... BD = baud rate divisor Table 13-8 shows the SCI baud rates that can be generated with a 4.9152-MHz bus clock when f selected as SCI clock source. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Table 13-7. SCI Baud Rate Selection Baud Rate Divisor (BD) 000 001 ...
Page 156
... Baud Rate (f = 4.9152 MHz) BUS 76,800 38,400 19,200 9600 4800 2400 1200 600 25,600 12,800 6400 3200 1600 800 400 200 19,200 9600 4800 2400 1200 600 300 150 5908 2954 1477 739 369 185 92 46 Freescale Semiconductor ...
Page 157
... SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing INTERNAL PULLUP DEVICE RESET PIN LOGIC SIM RESET STATUS REGISTER MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor STOP/WAIT CONTROL SIM COUNTER ÷ 2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL MASTER ...
Page 158
... Writing a 0 clears SBSW. POR PIN COP BCFE IF6 IF5 IF4 IF14 IF13 IF12 Unimplemented Figure 14-2. SIM I/O Register Summary SBSW (1) Note ILOP ILAD MODRST LVI IF3 IF2 IF1 IF11 IF10 IF9 IF8 IF16 Reserved Freescale Semiconductor Bit IF7 R 0 IF15 R 0 ...
Page 159
... In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor CGMXCLK CGMOUT Figure 14-3. System Clock Signals 14 ...
Page 160
... MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 160 14.4 SIM Counter), but an external reset does not. Each of shows the relative timing. VECT H Figure 14-4. External Reset Timing Figure 14-5. An internal reset can be caused by an illegal address, Figure 14-6. NOTE 14.7 SIM Registers. VECT L Freescale Semiconductor ...
Page 161
... The RST pin is driven low during the oscillator stabilization time. • The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES Figure 14-5. Internal Reset Timing ...
Page 162
... The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 162 32 32 CYCLES CYCLES Figure 14-7. POR Recovery on the RST pin disables the COP module. TST $FFFE $FFFF while the MCU is in monitor TST voltage falls to the V DD TRIPF Freescale Semiconductor ...
Page 163
... Non-maskable software interrupt instruction (SWI) • Reset • Break interrupts MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 14.6.2 Stop Mode 14.3.2 Active Resets from Internal Sources SIM Counter 18.3.1.1 Normal Monitor Mode). for details. The SIM counter is for counter control and ...
Page 164
... SP – – – – Figure 14-8 Interrupt Entry Timing SP – – – – 1 [7:0] PC – 1 [15:8] OPCODE Figure 14-9. Interrupt Recovery Timing Figure 14-8 shows VECT H VECT L START ADDR CCR V DATA H V DATA L OPCODE OPERAND Freescale Semiconductor ...
Page 165
... CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). See YES AS MANY INTERRUPTS AS EXIST ON CHIP MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Figure 14-10. FROM RESET BREAK I BIT SET? YES ...
Page 166
... A software interrupt pushes PC onto the stack. A software interrupt does not push PC – hardware interrupt does. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 166 CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI Interrupt Recognition Example . NOTE NOTE BACKGROUND ROUTINE Freescale Semiconductor ...
Page 167
... These flags indicate the presence of interrupt requests from the sources shown Interrupt request present interrupt request present Bit 0 and Bit 1 — Always read 0 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Table 14-3. Interrupt Sources Interrupt Source Reset SWI instruction IRQ pin ...
Page 168
... SIM break flag control register (SBFCR). MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 168 I13 I12 I11 I10 Reserved Reserved 2 1 Bit Table 14- Bit 0 0 I16 I15 Table 14-3. TIM2)). The SIM puts the Freescale Semiconductor ...
Page 169
... Previous data can be operand data or the WAIT opcode, depending on the last instruction. Figure 14-16 and Figure 14-17 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 14-15. Wait Mode Entry Timing show the timing for WAIT recovery. ...
Page 170
... To minimize stop current, all pins configured as inputs should be driven MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 170 $6E0B $6E0C $00FF $00FE $A6 $A6 $01 $ CYCLES CYCLES $A6 NOTE Figure 14-18 NOTE $00FD $00FC $6E RST VCT H RST VCT L shows stop mode entry timing. Freescale Semiconductor ...
Page 171
... Read: R Write: Reset Writing a 0 clears SBSW. Figure 14-20. Break Status Register (SBSR) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor STOP ADDR + 1 PREVIOUS DATA NEXT OPCODE Figure 14-18. Stop Mode Entry Timing STOP RECOVERY PERIOD STOP + 2 STOP + 2 Table 14-4 shows the mapping of these registers. ...
Page 172
... Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 172 PIN COP ILOP ILAD Bit 0 MODRST LVI Freescale Semiconductor ...
Page 173
... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 174
... System Integration Module (SIM) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 174 Freescale Semiconductor ...
Page 175
... If a port bit is configured for input, then an internal pullup device may be enabled for that port bit. The following paragraphs describe the operation of the SPI module. Refer to of the SPI I/O registers. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Figure 15-3 for a summary 175 ...
Page 176
... MONITOR MODULE MEMORY MAP MODULE CONFIGURATION REGISTER 1 MODULE CONFIGURATION REGISTER 2 MODULE PTA3/KBD3– (1) PTA0/KBD0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1), (2) PTC1 (1), (2) PTC0 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
Page 177
... SPI Status and Control $0011 Register (SPSCR) Write: See page 192. Reset: Read: SPI Data Register $0012 (SPDR) Write: See page 194. Reset: MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER RECEIVE DATA REGISTER SPR0 SPMSTR ...
Page 178
... MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 178 NOTE Figure 15-4. MISO MISO MOSI MOSI SPSCK SPSCK Register.) Through the SPSCK pin, the baud rate generator of the 15.12.1 SPI SLAVE MCU SHIFT REGISTER 15.6.2 Mode Fault Error. Freescale Semiconductor ...
Page 179
... The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 15.4 Transmission Formats. ...
Page 180
... The SS pin of the master is not shown but is assumed to be inactive. The SS MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 180 15.6.2 Mode Fault MSB BIT 6 BIT 5 BIT 4 BIT 3 MSB BIT 6 BIT 5 BIT 4 BIT 3 BYTE 1 BYTE 2 Figure 15-6. CPHA/SS Timing Error.) When CPHA = 0, the first BIT 2 BIT 1 LSB BIT 2 BIT 1 LSB BYTE 3 Freescale Semiconductor ...
Page 181
... This delay is no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 182
... SPSCK = BUS CLOCK ÷ 2; EARLIEST 2 POSSIBLE START POINTS LATEST SPSCK = BUS CLOCK ÷ 8; EARLIEST 8 POSSIBLE START POINTS EARLIEST SPSCK = BUS CLOCK ÷ 32; 32 POSSIBLE START POINTS SPSCK = BUS CLOCK ÷ 128; EARLIEST 128 POSSIBLE START POINTS BIT 6 BIT LATEST LATEST LATEST Freescale Semiconductor ...
Page 183
... For an already active slave, the load of the shift register cannot occur until the transmission is completed. This implies that a back-to-back write to the transmit data register is not possible. SPTE indicates when the next write can occur. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 184
... CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT, BUT NOT OVRF BIT. 8 BYTE 4 FAILS TO SET SPRF BIT BECAUSE OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST. 15-7 overflow occurs, all data Figure 15-12.) It Figure 15-10 shows how it is BYTE 4 8 Freescale Semiconductor ...
Page 185
... The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Figure 15-11 illustrates this process. Generally, to avoid this second BYTE 2 ...
Page 186
... MODF condition existing or else the flag is not cleared. 15.7 Interrupts Four SPI status flags can be enabled to generate CPU interrupt requests. See MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 186 NOTE 15.4 Transmission NOTE NOTE NOTE Table Formats. 15-1. Freescale Semiconductor ...
Page 187
... SPI transmitter empty (SPTE) — SPTE becomes set every time a byte transfers from the transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set, SPTE generates an SPTE CPU interrupt request. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Table 15-1. SPI Interrupts Request SPI transmitter CPU interrupt request ...
Page 188
... Chapter 14 System Integration Module (SIM). To allow software to clear status bits during a break interrupt, write BCFE status bit is cleared during the break state, it remains cleared when the MCU exits the break state. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 188 15.7 Interrupts. Freescale Semiconductor ...
Page 189
... SPSCK pin is the clock output slave MCU, the SPSCK pin is the clock input. In full-duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 2 C) capability (requiring software support master in a ...
Page 190
... Mode Fault Error.) Table 15-2. Table 15-2. SPI Configuration MODFEN SPI Configuration X Not enabled X Slave 0 Master without MODF 1 Master with MODF BYTE 3 For the state of Function of SS Pin General-purpose I/O; SS ignored by SPI Input-only to SPI General-purpose I/O; SS ignored by SPI Input-only to SPI Freescale Semiconductor ...
Page 191
... SPWOM — SPI Wired-OR Mode Bit This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins become open-drain outputs Wired-OR SPSCK, MOSI, and MISO pins 0 = Normal push-pull SPSCK, MOSI, and MISO pins MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 192
... This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears the ERRIE bit MODF and OVRF can generate CPU interrupt requests 0 = MODF and OVRF cannot generate CPU interrupt requests MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 192 OVRF MODF SPTE ERRIE Unimplemented 2 1 Bit 0 MODFEN SPR1 SPR0 Freescale Semiconductor 15.8 ...
Page 193
... In master mode, these read/write bits select one of four baud rates as shown in SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0. Table 15-3. SPI Master Baud Rate Selection SPR1 and SPR0 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE Baud Rate Divisor (BD ...
Page 194
... R7–R0/T7–T0 — Receive/Transmit Data Bits Do not use read-modify-write instructions on the SPI data register since the register read is not the same as the register written. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 194 Figure Unaffected by reset Figure 15-16. SPI Data Register (SPDR) NOTE 15- Bit Freescale Semiconductor ...
Page 195
... TBR2–TBR0. When the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt request. Interrupts must be acknowledged by writing the TACK bit. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE Figure 16-1, starts 195 ...
Page 196
... In stop mode, the timebase register is not accessible by the CPU. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 196 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 Figure 16-1. Timebase Block Diagram TBON TBMINT TBIF Freescale Semiconductor TBIE ...
Page 197
... TACK— Timebase Acknowledge Bit The TACK bit is a write-only bit and always reads as 0. Writing this bit clears TBIF, the timebase interrupt flag bit. Writing this bit has no effect Clear timebase interrupt flag effect MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 198
... This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption when its function is not necessary. The counter can be initialized by clearing and then setting this bit. Reset clears the TBON bit Timebase is enabled Timebase is disabled and the counter initialized to 0s. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 198 Freescale Semiconductor ...
Page 199
... COUNTER 16-BIT COMPARATOR TMODH:TMODL CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Figure 17 block diagram of the TIM. PRESCALER SELECT PS2 PS1 PS0 ELS0B ELS0A CH0F MS0A MS0B ELS1B ...
Page 200
... MONITOR MODULE MEMORY MAP MODULE CONFIGURATION REGISTER 1 MODULE CONFIGURATION REGISTER 2 MODULE PTA3/KBD3– (1) PTA0/KBD0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1), (2) PTC1 (1), (2) PTC0 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...