MC68HC11E0CFNE2 Freescale Semiconductor, MC68HC11E0CFNE2 Datasheet - Page 140

IC MCU 8BIT 2MHZ 52-PLCC

MC68HC11E0CFNE2

Manufacturer Part Number
MC68HC11E0CFNE2
Description
IC MCU 8BIT 2MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E0CFNE2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Ram Memory Size
512Byte
Cpu Speed
2MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Digital Ic Case Style
LCC
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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Timing Systems
9.4.10 Timer Interrupt Flag Register 2
Bits in this register indicate when certain timer system events have occurred. Coupled with the four
high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled or
interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position.
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
RTIF — Real-Time (Periodic) Interrupt Flag
PAOVF — Pulse Accumulator Overflow Interrupt Flag
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Bits [3:0] — Unimplemented
9.5 Real-Time Interrupt (RTI)
The real-time interrupt (RTI) feature, used to generate hardware interrupts at a fixed periodic rate, is
controlled and configured by two bits (RTR1 and RTR0) in the pulse accumulator control (PACTL)
register. The RTII bit in the TMSK2 register enables the interrupt capability. The four different rates
available are a product of the MCU oscillator frequency and the value of bits RTR[1:0]. Refer to
which shows the periodic real-time interrupt rates.
The clock source for the RTI function is a free-running clock that cannot be stopped or interrupted except
by reset. This clock causes the time between successive RTI timeouts to be a constant that is
140
Set when TCNT changes from $FFFF to $0000
Refer to
Refer to
Refer to
Always read 0
9.5 Real-Time Interrupt
9.7 Pulse
9.7 Pulse
Address:
Reset:
RTR[1:0]
Read:
Write:
0 0
0 1
1 0
1 1
Accumulator.
Accumulator.
$1025
Bit 7
TOF
Figure 9-20. Timer Interrupt Flag 2 Register (TFLG2)
0
E = 3 MHz
= Unimplemented
10.923 ms
21.845 ms
2.731 ms
5.461 ms
RTIF
6
0
M68HC11E Family Data Sheet, Rev. 5.1
(RTI).
PAOVF
Table 9-5. RTI Rates
5
0
E = 2 MHz
16.384 ms
32.768 ms
4.096 ms
8.192 ms
PAIF
4
0
3
0
E = 1 MHz
16.384 ms
32.768 ms
65.536 ms
8.192 ms
2
0
1
0
E = X MHz
(E/2
(E/2
(E/2
(E/2
Freescale Semiconductor
13
14
15
16
)
)
)
)
Bit 0
0
Table
9-5,

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