MC68HC11E0CFNE2 Freescale Semiconductor, MC68HC11E0CFNE2 Datasheet - Page 163

IC MCU 8BIT 2MHZ 52-PLCC

MC68HC11E0CFNE2

Manufacturer Part Number
MC68HC11E0CFNE2
Description
IC MCU 8BIT 2MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E0CFNE2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Ram Memory Size
512Byte
Cpu Speed
2MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Digital Ic Case Style
LCC
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC11E0CFNE2
Manufacturer:
FREESCALE
Quantity:
6 221
Part Number:
MC68HC11E0CFNE2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68HC11E0CFNE2R
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
10.12 MC68L11E9/E20 Peripheral Port Timing
Freescale Semiconductor
Frequency of operation
E-clock period
Peripheral data setup time
Peripheral data hold time
Delay time, peripheral data write
Port C input data setup time
Port C input data hold time
Delay time, E fall to STRB
Setup time, STRA asserted to E fall
Delay time, STRA asserted to port C data output valid
Hold time, STRA negated to port C data
3-state hold time
1. V
2. Ports C and D timing is valid for active drive. (CWOM and DWOM bits are not set in PIOC and SPCR registers, respec-
3. If this setup time is met, STRB acknowledges in the next cycle. If it is not met, the response may be delayed one more cycle.
E-clock frequency
MCU read of ports A, C, D, and E
MCU read of ports A, C, D, and E
t
t
PWD
DEB
otherwise noted
tively.)
DD
MCU writes to port A
MCU writes to ports B, C, and D
= 1/4 t
= 1/4 t
= 3.0 Vdc to 5.5 Vdc, V
CYC
CYC
+ 150 ns
+ 150 ns
Characteristic
SS
= 0 Vdc, T
(3)
(1) (2)
Figure 10-7. Port Read Timing Diagram
M68HC11E Family Data Sheet, Rev. 5.1
A
= T
L
to T
H
, all timing is shown with respect to 20% V
Symbol
t
t
t
PDSU
t
t
t
t
t
t
PWD
CYC
PDH
PCD
PCH
DEB
AES
PCZ
t
t
f
IS
IH
o
1000
Min
100
100
dc
50
60
10
0
1.0 MHz
MC68L11E9/E20 Peripheral Port Timing
Max
250
400
400
100
150
1.0
Min
500
100
100
DD
dc
50
60
10
0
2.0 MHz
and 70% V
Max
250
275
275
100
150
2.0
DD
, unless
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
163

Related parts for MC68HC11E0CFNE2