MC68HC11E0CFNE2 Freescale Semiconductor, MC68HC11E0CFNE2 Datasheet - Page 44

• Manufacturer Part Number: MC68HC11E0CFNE2
• Description: IC MCU 8BIT 2MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Ram Memory Size: 512Byte
• Cpu Speed: 2MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Digital Ic Case Style: LCC
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Operating Modes and On-Chip Memory
EE[3:0] — EEPROM Mapping Bits
44
EE[3:0] apply only to MC68HC811E2 and allow the 2048 bytes of EEPROM to be remapped to any
4-Kbyte boundary. See
Resets:
U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset,
but the function of COP is controlled by the DISR bit in TEST1 register.
Single chip:
Expanded:
Bootstrap:
Address:
Figure 2-11. MC68HC811E2 System Configuration Register (CONFIG)
Read:
Write:
Test:
$103F
Bit 7
EE3
U
U
1
1
Table
= Unimplemented
2-3.
EE2
EE[3:0]
U
U
6
1
1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
M68HC11E Family Data Sheet, Rev. 5.1
Table 2-3. EEPROM Mapping
EE1
U
U
5
1
1
EE0
U
U
4
1
1
EEPROM Location
$C800–$CFFF
$D800–$DFFF
$A800–$AFFF
$B800–$BFFF
$E800–$EFFF
$F800–$FFFF
$0800–$0FFF
$1800–$1FFF
$2800–$2FFF
$3800–$3FFF
$4800–$4FFF
$5800–$5FFF
$6800–$6FFF
$7800–$7FFF
$8800–$8FFF
$9800–$9FFF
NOSEC
U
U
3
1
1
NOCOP
U(L)
U(L)
U
U
2
1
1
1
1
1
Freescale Semiconductor
EEON
Bit 0
U
1
1
0