MC68HC11E0CFNE2 Freescale Semiconductor, MC68HC11E0CFNE2 Datasheet - Page 67

IC MCU 8BIT 2MHZ 52-PLCC

MC68HC11E0CFNE2

Manufacturer Part Number
MC68HC11E0CFNE2
Description
IC MCU 8BIT 2MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E0CFNE2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Ram Memory Size
512Byte
Cpu Speed
2MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Digital Ic Case Style
LCC
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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At the end of the interrupt service routine, an return-from interrupt (RTI) instruction is executed. The RTI
instruction causes the saved registers to be pulled off the stack in reverse order. Program execution
resumes at the return address.
Certain instructions push and pull the A and B accumulators and the X and Y index registers and are often
used to preserve program context. For example, pushing accumulator A onto the stack when entering a
subroutine that uses accumulator A and then pulling accumulator A off the stack just before leaving the
subroutine ensures that the contents of a register will be the same after returning from the subroutine as
it was before starting the subroutine.
Freescale Semiconductor
JSR, JUMP TO SUBROUTINE
BSR, BRANCH TO SUBROUTINE
RTS, RETURN FROM
SUBROUTINE
INDEXED, X
INDEXED, Y
INDEXED, Y
DIRECT
PC
PC
MAIN PROGRAM
MAIN PROGRAM
$8D = BSR
RTN
RTN
RTN
RTN
$39 = RTS
PC
PC
PC
PC
NEXT MAIN INSTR.
NEXT MAIN INSTR.
NEXT MAIN INSTR.
NEXT MAIN INSTR.
MAIN PROGRAM
MAIN PROGRAM
MAIN PROGRAM
MAIN PROGRAM
$AD = JSR
$AD = JSR
$BD = PRE
$9D = JSR
$18 = PRE
hh
dd
ff
ff
ll
È
È
SP–2
SP–1
SP+1
SP+2
SP
SP
7
7
È
Figure 4-2. Stacking Operations
M68HC11E Family Data Sheet, Rev. 5.1
SP–2
SP–1
STACK
STACK
SP
RTN
RTN
RTN
RTN
7
H
L
H
L
STACK
RTN
RTN
0
0
H
L
0
LEGEND:
RTN
RTN
RTN = ADDRESS OF NEXT INSTRUCTION IN MAIN PROGRAM TO
RTI, RETURN FROM INTERRUPT
SWI, SOFTWARE INTERRUPT
WAI, WAIT FOR INTERRUPT
dd = 8-BIT DIRECT ADDRESS ($0000–$00FF) (HIGH BYTE ASSUMED
hh = HIGH-ORDER BYTE OF 16-BIT EXTENDED ADDRESS
È = STACK POINTER POSITION AFTER OPERATION IS COMPLETE
H
ff = 8-BIT POSITIVE OFFSET $00 (0) TO $FF (255) IS ADDED TO INDEX
L
ll = LOW-ORDER BYTE OF 16-BIT EXTENDED ADDRESS
rr= SIGNED RELATIVE OFFSET $80 (–128) TO $7F (+127) (OFFSET
= MOST SIGNIFICANT BYTE OF RETURN ADDRESS
= LEAST SIGNIFICANT BYTE OF RETURN ADDRESS
PC
PC
PC
BE EXECUTED UPON RETURN FROM SUBROUTINE
TO BE $00)
RELATIVE TO THE ADDRESS FOLLOWING THE MACHINE CODE
OFFSET BYTE)
INTERRUPT ROUTINE
MAIN PROGRAM
MAIN PROGRAM
$3F = SWI
$3E = WAI
$3B = RTI
È
È
SP+1
SP+2
SP+3
SP+4
SP+5
SP+6
SP+7
SP+8
SP+9
SP–9
SP–8
SP–7
SP–6
SP–5
SP–4
SP–3
SP–2
SP–1
SP
SP
7
7
STACK
STACK
ACCB
ACCA
ACCB
ACCA
RTN
RTN
RTN
RTN
CCR
CCR
IX
IY
IX
IY
IX
IY
IX
IY
H
L
H
L
H
L
H
L
CPU Registers
H
H
L
L
0
0
67

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