MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 42

• Manufacturer Part Number: MC68HC11E0CFNE3
• Description: IC MCU 8BIT 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Ram Memory Size: 512Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Digital Ic Case Style: LCC
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

CONFIG — System Configuration
PSEL[3:0] — Priority Select Bits
4.2.2 System Initialization
4.2.2.1 CONFIG Register
Bits [7:3] and 0 — Not implemented
NOCOP — COP System Disable
ROMON — ROM Enable
4-8
RESET:
Refer to SECTION 5 RESETS AND INTERRUPTS.
Registers and bits that control initialization and the basic configuration of the MCU are
protected against writes except under special circumstances. The protection mecha-
nism, overridden in special operating modes, permits writing these bits only within the
first 64 bus cycles after any reset, and then only once after each reset. If the MCU is
going to be changed to a normal mode after being reset in a special mode, write to the
protected registers before writing the SMOD control bit to zero.
The CONFIG register consists of static latches that control the startup configuration of
the MCU. CONFIG is writable only once in expanded and single-chip modes (SMOD
= 0). In these modes, the COP watchdog timer is enabled out of reset.
Always read zero
This bit is cleared out of reset in normal modes (COP enabled). Refer to SECTION 5
RESETS AND INTERRUPTS.
In all modes, ROMON is forced to one out of reset. Writable once in normal modes and
writable at any time in special modes.
0 = COP system enabled
1 = COP system disabled
0 = ROM removed from the memory map
1 = ROM present in the memory map
Single-Chip
Expanded
Boot
Special Test
Bit 7
Mode
0
0
Freescale Semiconductor, Inc.
6
0
0
OPERATING MODES AND ON-CHIP MEMORY
IRVNE Out
For More Information On This Product,
of Reset
0
0
0
1
Go to: www.freescale.com
5
0
0
E Clock Out
of Reset
On
On
On
On
4
0
0
3
0
0
IRV Out of
Reset
Off
Off
Off
On
NOCOP
—
2
Affects Only
ROMON
IRVNE
IRV
IRV
TECHNICAL DATA
—
E
E
1
$003F
Bit 0
0
0