MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 45

• Manufacturer Part Number: MC68HC11E0CFNE3
• Description: IC MCU 8BIT 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Ram Memory Size: 512Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Digital Ic Case Style: LCC
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

5.1 Resets
5.1.1 Power-On Reset
5.1.2 External Reset (RESET)
5.1.3 COP Reset
TECHNICAL DATA
Resets and interrupt operations load the program counter with a vector that points to
a new location from which instructions are to be fetched. A reset immediately stops
execution of the current instruction and forces the program counter to a known starting
address. Internal registers and control bits are initialized so the MCU can resume ex-
ecuting instructions. An interrupt temporarily suspends normal program execution
while an interrupt service routine is being executed. After an interrupt has been ser-
viced, the main program resumes as if there had been no interruption.
There are four possible sources of reset. Power-on reset (POR) and external reset
share the normal reset vector. The computer operating properly (COP) system and the
clock monitor each has its own vector.
A positive transition on V
power-up conditions. POR cannot be used to detect drops in power supply voltages.
A 4064 t
clock generator to stabilize. If RESET is at logical zero at the end of 4064 t
CPU remains in the reset condition until goes to logical one.
It is important to protect the MCU during power transitions. Most M68HC11 systems
need an external circuit that holds the RESET pin low whenever V
imum operating level. This external voltage level detector, or other external reset cir-
cuits, are the usual source of reset in a system. The POR circuit only initializes internal
circuitry during cold starts. Refer to Figure 2-3.
The CPU distinguishes between internal and external reset conditions by sensing
whether the reset pin rises to a logic one in less than two E-clock cycles after an inter-
nal device releases reset. When a reset condition is sensed, the RESET pin is driven
low by an internal device for four E-clock cycles, then released. Two E-clock cycles
later it is sampled. If the pin is still held low, the CPU assumes that an external reset
has occurred. If the pin is high, it indicates that the reset was initiated internally by ei-
ther the COP system or the clock monitor. It is not advisable to connect an external
resistor capacitor (RC) power-up delay circuit to the reset pin of M68HC11 devices be-
cause the circuit charge time constant can cause the device to misinterpret the type of
reset that occurred.
The MCU includes a COP system to help protect against software failures. When the
CYC
(internal clock cycle) delay after the oscillator becomes active allows the
Freescale Semiconductor, Inc.
For More Information On This Product,
RESETS AND INTERRUPTS
DD
generates a power-on reset (POR), which is used only for
RESETS AND INTERRUPTS
Go to: www.freescale.com
SECTION 5
DD
is below the min-
CYC
, the
5-1