MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 46

• Manufacturer Part Number: MC68HC11E0CFNE3
• Description: IC MCU 8BIT 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Ram Memory Size: 512Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Digital Ic Case Style: LCC
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

COPRST — Am/Reset COP Timer Circuitry
5.1.4 Clock Monitor Reset
5-2
RESET:
COP is enabled, the software is responsible for keeping a free-running watchdog timer
from timing out. When the software is no longer being executed in the intended se-
quence, a system reset is initiated.
The state of the NOCOP bit in the CONFIG register determines whether the COP sys-
tem is enabled or disabled. In normal modes, COP is enabled out of reset and does
not depend on software action. To disable the COP system, set the NOCOP bit in the
CONFIG register. In the special test and bootstrap operating modes, the COP system
is initially inhibited by the disable resets (DISR) control bit in the TEST1 register. The
DISR bit can subsequently be written to zero to enable COP resets.
The COP timer rate control bits CR[1:0] in the OPTION register determine the COP
time-out period. The system E clock is divided by 2
tor shown in Table 5-1. After reset, these bits are zero, which selects the fastest time-
out period. In normal operating modes, these bits can only be written once within 64
bus cycles after reset.
Complete the following reset sequence to service the COP timer. Write $55 to CO-
PRST to arm the COP timer clearing mechanism. Then write $AA to COPRST to clear
the COP timer. Performing instructions between these two steps is possible as long as
both steps are completed in the correct sequence before the timer times out.
The clock monitor circuit is based on an internal RC time delay. If no MCU clock edges
are detected within this RC time delay, the clock monitor can optionally generate a sys-
tem reset. The clock monitor function is enabled or disabled by the CME control bit in
the OPTION register. The presence of a time-out is determined by the RC delay, which
allows the clock monitor to operate without any MCU clocks.
Clock monitor is used as a backup for the COP system. Because the COP needs a
clock to function, it is disabled when the clocks stop. Therefore, the clock monitor sys-
tem can detect clock failures not detected by the COP system.
CR[1:0]
0 0
0 1
1 0
1 1
Bit 7
7
0
Divide
E/2
E =
By
16
64
1
4
15
Freescale Semiconductor, Inc.
6
6
0
For More Information On This Product,
XTAL = 4.0 MHz
Table 5-1 COP Time-out
RESETS AND INTERRUPTS
–0/+32.8 ms
131.072 ms
524.288 ms
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32.768 ms
5
5
0
Time-out
2.097 sec
1.0 MHz
4
4
0
XTAL = 8.0 MHz
–0/+16.4 ms
262.140 ms
3
3
0
15
16.384 ms
65.536 ms
1.049 sec
Time-out
2.0 MHz
and then further scaled by a fac-
2
2
0
XTAL = 12.0 MHz
TECHNICAL DATA
1
1
0
–0/+10.9 ms
10.923 ms
43.691 ms
174.76 ms
699.05 ms
Time-out
3.0 MHz
$003A
Bit 0
0
0