MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 71

• Manufacturer Part Number: MC68HC11E0CFNE3
• Description: IC MCU 8BIT 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Ram Memory Size: 512Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Digital Ic Case Style: LCC
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

SCDR — SCI Data Register
SCCR1 — SCI Control Register 1
7.5 SCI Error Detection
7.6 SCI Registers
7.6.1 Serial Communications Data Register (SCDR)
7.6.2 Serial Communications Control Register 1 (SCCR1)
R8 — Receive Data Bit 8
TECHNICAL DATA
RESET:
RESET:
Three error conditions, SCDR overrun, received bit noise, and framing can occur dur-
ing generation of SCI system interrupts. Three bits (OR, NF, and FE) in the serial com-
munications status register (SCSR) indicate if one of these error conditions exists. The
overrun error (OR) bit is set when the next byte is ready to be transferred from the re-
ceive shift register to the SCDR and the SCDR is already full (RDRF bit is set). When
an overrun error occurs, the data that caused the overrun is lost and the data that was
already in SCDR is not disturbed. The OR is cleared when the SCSR is read (with OR
set), followed by a read of the SCDR.
The noise flag (NF) bit is set if there is noise on any of the received bits, including the
start and stop bits. The NF bit is not set until the RDRF flag is set. The NF bit is cleared
when the SCSR is read (with FE equal to one) followed by a read of the SCDR.
When no stop bit is detected in the received data character, the framing error (FE) bit
is set. FE is set at the same time as the RDRF. If the byte received causes both fram-
ing and overrun errors, the processor only recognizes the overrun error. The framing
error flag inhibits further transfer of data into the SCDR until it is cleared. The FE bit is
cleared when the SCSR is read (with FE equal to one) followed by a read of the SCDR.
There are five addressable registers in the SCI.
SCDR is a parallel register that performs two functions. It is the receive data register
when it is read, and the transmit data register when it is written. Reads access the re-
ceive data buffer and writes access the transmit data buffer. Receive and transmit are
double buffered.
*U = Unaffected
The SCCR1 register provides the control bits that determine word length and select
the method used for the wake-up feature.
If M bit is set, R8 stores the ninth bit in the receive data character.
R7/T7
Bit 7
Bit 7
R8
U*
U
R6/T6
T8
Freescale Semiconductor, Inc.
U
U
6
6
For More Information On This Product,
SERIAL COMMUNICATIONS INTERFACE
R5/T5
Go to: www.freescale.com
U
5
5
0
0
R4/T4
M
U
4
4
0
WAKE
R3/T3
U
3
3
0
R2/T2
U
2
2
0
0
R1/T1
U
1
1
0
0
$002C
$002F
R0/T0
Bit 0
Bit 0
U
0
0
7-5