MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 81

• Manufacturer Part Number: MC68HC11E0CFNE3
• Description: IC MCU 8BIT 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Ram Memory Size: 512Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Digital Ic Case Style: LCC
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

8.2.1 Clock Phase and Polarity Controls
8.3 SPI Signals
TECHNICAL DATA
(CPHA = 0)
(CPHA = 1 )
Software can select one of four combinations of serial clock phase and polarity using
two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL
control bit, which selects an active high or active low clock, and has no significant ef-
fect on the transfer format. The clock phase (CPHA) control bit selects one of two dif-
ferent transfer formats. The clock phase and polarity should be identical for the master
SPI device and the communicating slave device. In some cases, the phase and polar-
ity are changed between transfers to allow a master device to communicate with pe-
ripheral slaves having different requirements.
When CPHA equals zero, the slave select (SS) line must be negated and reasserted
between each successive serial byte. Also, if the slave writes data to the SPI data reg-
ister (SPDR) while SS is active low, a write collision error results.
When CPHA equals one, the SS line can remain low between successive transfers.
The following paragraphs contain descriptions of the four SPI signals: master in slave
out (MISO), master out slave in (MOSI), serial clock (SCK), and SS.
1. SS ASSERTED
2. MASTER WRITES TO SPDR
3. FIRST SCK EDGE
4. SPIF SET
5. SS NEGATED
SAMPLE INPUT
SAMPLE INPUT
SCK (CPOL = 0)
SCK (CPOL = 1)
SS (TO SLAVE)
SCK CYCLE #
DATA OUT
DATA OUT
1
2
MSB
Freescale Semiconductor, Inc.
3
For More Information On This Product,
Figure 8-2 SPI Transfer Format
MSB
1
SERIAL PERIPHERAL INTERFACE
6
Go to: www.freescale.com
2
6
SLAVE CPHA=0 TRANSFER IN PROGRESS
SLAVE CPHA=1 TRANSFER IN PROGRESS
5
MASTER TRANSFER IN PROGRESS
3
5
4
4
4
3
5
3
2
6
2
1
7
1
LSB
8
SPI TRANSFER FORMAT 1
LSB
4
5
8-3