MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 99

• Manufacturer Part Number: MC68HC11E0CFNE3
• Description: IC MCU 8BIT 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Ram Memory Size: 512Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Digital Ic Case Style: LCC
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

9.4.1 Timer Interrupt Mask 2 Register
TOI — Timer Overflow Interrupt Enable
RTII — Real-time Interrupt Enable
PAOVI — Pulse Accumulator Overflow Interrupt Enable
PAII — Pulse Accumulator Input Edge
9.4.1 Timer Interrupt Flag 2 Register
TECHNICAL DATA
TMSK2 — Timer Interrupt Mask 2
RESET:
The clock source for the RTI function is a free-running clock that cannot be stopped or
interrupted except by reset. This clock causes the time between successive RTI time-
outs to be a constant that is independent of the software latencies associated with flag
clearing and service. For this reason, an RTI period starts from the previous time-out,
not from when RTIF is cleared.
Every time-out causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt
request is generated. After reset, one entire real-time interrupt period elapses before
the RTIF flag is set for the first time. Refer to the TMSK2, TFLG2, and PACTL regis-
ters.
This register contains the real-time interrupt enable bits.
Refer to 9.6 Pulse Accumulator.
Refer to 9.6 Pulse Accumulator.
Bits of this register indicate the occurrence of timer system events. Coupled with the
four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate
in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in
TMSK2 in the same position.
RTR[1:0]
Refer to 9.3 Output Compare.
0 = RTIF interrupts disabled
1 = Interrupt requested when RTIF is set to one
0 0
0 1
1 0
1 1
Bit 7
TOI
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in
TMSK2 enable the corresponding interrupt sources.
0
RTII
E = 1 MHz
10.923 ms
21.845 ms
Freescale Semiconductor, Inc.
2.731 ms
5.461 ms
6
0
For More Information On This Product,
PAOVI
Go to: www.freescale.com
5
0
TIMING SYSTEM
E = 2 MHz
16.384 ms
32.768 ms
4.096 ms
8.192 ms
PAII
4
0
NOTE
3
0
0
E = 3 MHz
16.384 ms
32.768 ms
65.536 ms
8.192 ms
2
0
0
PR1
1
0
E = X MHz
(E/2
(E/2
(E/2
(E/2
13
14
15
16
)
)
)
)
$0024
Bit 0
PR0
0
9-13