MC68HC11E1CFNE2 Freescale Semiconductor, MC68HC11E1CFNE2 Datasheet - Page 111

• Manufacturer Part Number: MC68HC11E1CFNE2
• Description: IC MCU 8BIT 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 38
• Interface: SCI/SPI
• Memory Type: ROM
• Number Of Bits: 8
• Package Type: 52-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 2MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

7.7.3 Serial Communications Control Register 2
The SCCR2 register provides the control bits that enable or disable individual SCI functions.
TIE — Transmit Interrupt Enable Bit
TCIE — Transmit Complete Interrupt Enable Bit
RIE — Receiver Interrupt Enable Bit
ILIE — Idle-Line Interrupt Enable Bit
TE — Transmitter Enable Bit
RE — Receiver Enable Bit
RWU — Receiver Wakeup Control Bit
SBK — Send Break
Freescale Semiconductor
When TE goes from 0 to 1, one unit of idle character time (logic 1) is queued as a preamble.
At least one character time of break is queued and sent each time SBK is written to 1. As long as the
SBK bit is set, break characters are queued and sent. More than one break may be sent if the
transmitter is idle at the time the SBK bit is toggled on and off, as the baud rate clock edge could occur
between writing the 1 and writing the 0 to SBK.
0 = TDRE interrupts disabled
1 = SCI interrupt requested when TDRE status flag is set
0 = TC interrupts disabled
1 = SCI interrupt requested when TC status flag is set
0 = RDRF and OR interrupts disabled
1 = SCI interrupt requested when RDRF flag or the OR status flag is set
0 = IDLE interrupts disabled
1 = SCI interrupt requested when IDLE status flag is set
0 = Transmitter disabled
1 = Transmitter enabled
0 = Receiver disabled
1 = Receiver enabled
0 = Normal SCI receiver
1 = Wakeup enabled and receiver interrupts inhibited
0 = Break generator off
1 = Break codes generated
Address:
Reset:
Read:
Write:
Figure 7-5. Serial Communications Control Register 2 (SCCR2)
$102D
Bit 7
TIE
0
TCIE
6
0
M68HC11E Family Data Sheet, Rev. 5.1
RIE
5
0
ILIE
4
0
TE
3
0
RE
2
0
RWU
1
0
Bit 0
SBK
0
SCI Registers
111