MC68HC11E1CFNE2 Freescale Semiconductor, MC68HC11E1CFNE2 Datasheet - Page 173

• Manufacturer Part Number: MC68HC11E1CFNE2
• Description: IC MCU 8BIT 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 38
• Interface: SCI/SPI
• Memory Type: ROM
• Number Of Bits: 8
• Package Type: 52-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 2MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

Freescale Semiconductor
CPOL = 1
CPOL = 0
OUTPUT
CPOL = 1
OUTPUT
CPOL = 0
OUTPUT
OUTPUT
INPUT
INPUT
Note: This first clock edge is generated internally but is not seen at the SCK pin.
Note: This first clock edge is generated internally but is not seen at the SCK pin.
INPUT
INPUT
MISO
MISO
MOSI
INPUT
INPUT
MOSI
SCK
SCK
SCK
SCK
SS
SS
SEE NOTE
SEE NOTE
Figure 10-15. SPI Timing Diagram (Sheet 1 of 2)
4
5
6
MASTER MSB OUT
SS IS HELD HIGH ON MASTER.
MASTER MSB OUT
MSB IN
10 (REF)
MSB IN
M68HC11E Family Data Sheet, Rev. 5.1
1
A) SPI Master Timing (CPHA = 0)
B) SPI Master Timing (CPHA = 1)
SS IS HELD HIGH ON MASTER.
7
4
5
4
5
1
4
5
BIT 6 . . . 1
11
BIT 6 . . . 1
11
MC68L11E9/E20 Serial Peirpheral Interface Characteristics
BIT 6 . . . 1
BIT 6 . . . 1
6
10
10
MASTER LSB OUT
LSB IN
MASTER LSB OUT
LSB IN
SEE NOTE
SEE NOTE
7
11 (REF)
11 (REF)
173