MC68HC11E1CFNE2 Freescale Semiconductor, MC68HC11E1CFNE2 Datasheet - Page 34

• Manufacturer Part Number: MC68HC11E1CFNE2
• Description: IC MCU 8BIT 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 38
• Interface: SCI/SPI
• Memory Type: ROM
• Number Of Bits: 8
• Package Type: 52-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 2MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

Operating Modes and On-Chip Memory
34
$100A
$100B
$100C
$1000
$1001
$1002
$1003
$1004
$1005
$1006
$1007
$1008
$1009
Addr.
Output Compare 1 Mask Register
Timer Compare Force Register
Port C Data Direction Register
Port D Data Direction Register
Parallel I/O Control Register
Register Name
Port C Latched Register
Port C Data Register
Port D Data Register
Port A Data Register
Port B Data Register
Port E Data Register
Figure 2-7. Register and Control Bit Assignments (Sheet 1 of 6)
See page 102.
See page 100.
See page 100.
See page 100.
See page 101.
See page 135.
See page 136.
See page 98.
See page 99.
See page 99.
See page 99.
(PORTCL)
Reserved
Reserved
(CFORC)
(PORTC)
(PORTD)
(PORTA)
(PORTB)
(PORTE)
(DDRC)
(DDRD)
(OC1M)
(PIOC)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
M68HC11E Family Data Sheet, Rev. 5.1
I = Indeterminate after reset
DDRC7
OC1M7
FOC1
STAF
PCL7
Bit 7
PA7
PC7
PB7
PE7
R
R
U
0
0
0
0
0
0
0
I
= Unimplemented
DDRC6
OC1M6
FOC2
PCL6
STAI
PA6
PC6
PB6
PE6
R
R
U
6
0
0
0
0
0
0
0
0
DDRC5
DDRD5
OC1M5
CWOM
FOC3
PCL5
PA5
PC5
PB5
PD5
PE5
R
R
5
0
0
0
0
0
0
0
I
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
DDRC4
DDRD4
OC1M4
HNDS
FOC4
PCL4
PA4
PC4
PB4
PD4
PE4
R
R
R
4
0
0
0
0
0
0
0
I
= Reserved
DDRC3
DDRD3
OC1M3
FOC5
PCL3
PA3
PC3
PB3
PD3
PE3
OIN
R
R
3
0
0
0
0
0
0
I
I
DDRC2
DDRD2
U = Unaffected
PCL2
PC2
PD2
PA2
PLS
PB2
PE2
Freescale Semiconductor
R
U
R
2
0
0
0
0
0
I
I
DDRC1
DDRD1
PCL1
EGA
PA1
PC1
PB1
PD1
PE1
R
R
1
1
0
0
0
0
0
I
I
DDRC0
DDRD0
PCL0
INVB
Bit 0
PA0
PC0
PB0
PD0
PE0
R
R
1
0
0
0
0
0
I
I