MC68HC711D3CFNE2 Freescale Semiconductor, MC68HC711D3CFNE2 Datasheet - Page 104

• Manufacturer Part Number: MC68HC711D3CFNE2
• Description: IC MCU 8BIT 3MHZ 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711D3CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 26
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

9.6.3 Pulse Accumulator Status and Interrupt Bits
PAOVI and PAOVF — Pulse Accumulator Interrupt Enable and Overflow Flag
PAII and PAIF — Pulse Accumulator Input Edge Interrupt Enable and Flag
9-18
PACNT — Pulse Accumulator Count
TMSK2 — Timer Interrupt Mask 2
TFLG2 — Timer Interrupt Flag 2
RESET:
RESET:
The pulse accumulator control bits, PAOVI and PAII, PAOVF, and PAIF are located
within timer registers TMSK2 and TFLG2.
The PAOVF status bit is set each time the pulse accumulator count rolls over from $FF
to $00. To clear this status bit, write a one in the corresponding data bit position (bit 5)
of the TFLG2 register. The PAOVI control bit allows configuring the pulse accumulator
overflow for polled or interrupt-driven operation and does not affect the state of
PAOVF. When PAOVI is zero, pulse accumulator overflow interrupts are inhibited, and
the system operates in a polled mode, which requires PAOVF to be polled by user soft-
ware to determine when an overflow has occurred. When the PAOVI control bit is set,
a hardware interrupt request is generated each time PAOVF is set. Before leaving the
interrupt service routine, software must clear PAOVF by writing to the TFLG2 register.
The PAIF status bit is automatically set each time a selected edge is detected at the
PA7/PAI/OC1 pin. To clear this status bit, write to the TFLG2 register with a one in the
corresponding data bit position (bit 4). The PAII control bit allows configuring the pulse
accumulator input edge detect for polled or interrupt-driven operation but does not af-
fect setting or clearing the PAIF bit. When PAII is zero, pulse accumulator input inter-
rupts are inhibited, and the system operates in a polled mode. In this mode, the PAIF
bit must be polled by user software to determine when an edge has occurred. When
the PAII control bit is set, a hardware interrupt request is generated each time PAIF is
set. Before leaving the interrupt service routine, software must clear PAIF by writing to
the TFLG register.
Bit 7
Bit 7
Bit 7
Bit 7
TOF
TOI
0
0
RTIF
RTII
Freescale Semiconductor, Inc.
6
6
6
0
6
0
For More Information On This Product,
PAOVF
PAOVI
Go to: www.freescale.com
5
5
5
0
5
0
TIMING SYSTEM
PAIF
PAII
4
4
4
0
4
0
3
3
3
0
0
3
0
0
2
2
2
0
0
2
0
0
TECHNICAL DATA
PR1
1
1
1
0
1
0
0
$0027
$0024
$0025
Bit 0
Bit 0
Bit 0
Bit 0
PR0
0
0
0