MC68HC711D3CFNE2 Freescale Semiconductor, MC68HC711D3CFNE2 Datasheet - Page 85

• Manufacturer Part Number: MC68HC711D3CFNE2
• Description: IC MCU 8BIT 3MHZ 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711D3CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 26
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

SPSR — Serial Peripheral Status Register
SPDR — SPI Data Register
8.5.2 Serial Peripheral Status
SPIF — SPI Transfer Complete Flag
WCOL — Write Collision
Bit 5 — Not implemented
MODF — Mode Fault
Bits [3:0] — Not implemented
8.5.3 Serial Peripheral Data I/O
TECHNICAL DATA
RESET:
SPIF is set upon completion of data transfer between the processor and the external
device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated.
To clear the SPIF bit, read the SPSR with SPIF set, then access the SPDR. Unless
SPSR is read (with SPIF set) first, attempts to write SPDR are inhibited.
Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) fol-
lowed by an access of SPDR. Refer to 8.3.4 Slave Select and 8.4 SPI System Errors.
Always reads zero
To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Refer
to 8.3.4 Slave Select and 8.4 SPI System Errors.
Always read zero
The SPDR is used when transmitting or receiving data on the serial bus. Only a write
to this register initiates transmission or reception of a byte, and this only occurs in the
master device. At the completion of transferring a byte of data, the SPIF status bit is
set in both the master and slave devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss
of the byte that caused the overrun, the first SPIF must be cleared by the time a second
transfer of data from the shift register to the read buffer is initiated.
0 = No write collision
1 = Write collision
0 = No mode fault
1 = Mode fault
SPIF
Bit 7
Bit 7
Bit 7
SPI is double buffered in and single buffered out.
0
WCOL
Freescale Semiconductor, Inc.
6
0
6
6
For More Information On This Product,
SERIAL PERIPHERAL INTERFACE
Go to: www.freescale.com
5
0
0
5
5
MODF
4
0
4
4
NOTE
3
0
0
3
3
2
0
0
2
2
1
0
0
1
1
$002A
$0029
Bit 0
Bit 0
Bit 0
0
0
8-7