M30626FJPFP#D5C Renesas Electronics America, M30626FJPFP#D5C Datasheet - Page 134

• Manufacturer Part Number: M30626FJPFP#D5C
• Description: MCU 3/5V 512K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPFP#D5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 12.8
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP
time of acceptance of an interrupt request, is even or odd. If the stack pointer
the PC are saved,16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 12.8 shows the
Operation of Saving Register.
NOTES:
1.When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated by the
Jan 10, 2006
U flag. Otherwise, it is the ISP.
Operation of Saving Register
(1) SP contains even number
[SP] − 5 (Odd)
[SP] − 4 (Even)
[SP] − 3(Odd)
[SP] − 2 (Even)
[SP] − 1(Odd)
[SP]
(2) SP contains odd number
[SP] − 5 (Even)
[SP] − 4(Odd)
[SP] − 3 (Even)
[SP] − 2(Odd)
[SP] − 1 (Even)
[SP]
PCH : 4 high-order bits of PC
PCM : 8 middle-order bits of PC
PCL
NOTES :
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged.
Address
Address
(Odd)
After registers are saved, the SP content is [SP] minus 4.
(Even)
: 8 low-order bits of PC
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FLGH
FLGH
Stack
Stack
FLGL
FLGL
PCM
PCM
PCL
PCL
PCH
PCH
FLGH : 4 high-order bits of FLG
FLGL : 8 low-order bits of FLG
Sequence in which order
registers are saved
Sequence in which order
registers are saved
Finished saving registers
in two operations.
Finished saving registers
in four operations.
(2) Saved simultaneously,
(1) Saved simultaneously,
(3)
(4)
(1)
(2)
all 16 bits
all 16 bits
Saved, 8 bits at a time
(1)
is even, the FLG register and
12. Interrupt
(1)
, at the