M30626FJPFP#D5C Renesas Electronics America, M30626FJPFP#D5C Datasheet - Page 143

• Manufacturer Part Number: M30626FJPFP#D5C
• Description: MCU 3/5V 512K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPFP#D5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
14. DMAC
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from
the source address to the destination address. The DMAC uses the same data bus as used by the CPU. Because the
DMAC has higher priority of bus control than the CPU and because it makes use of a cycle steal method, it can transfer
one word (16 bits) or one byte (8 bits) of data within a very short time after a DMA request is generated. Figure 14.1
shows the DMAC Block Diagram. Table 14.1 lists the DMAC Specifications. Figures 14.2 to 14.4 shows the DMAC-
related registers.
Figure 14.1
A DMA request is generated by a write to the DSR bit in the DMiSL register (i = 0 to 1), as well as by an interrupt
request which is generated by any function specified by the DMS and DSEL3 to DSEL0 bits in the DMiSL register.
However, unlike in the case of interrupt requests, DMA requests are not affected by the I flag and the interrupt control
register, so that even when interrupt requests are disabled and no interrupt request can be accepted, DMA requests are
always accepted. Furthermore, because the DMAC does not affect interrupts, the IR bit in the interrupt control register
does not change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON register = 1
(DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA transfer cycle, the
number of transfer requests generated and the number of times data is transferred may not match. Refer to 14.4 DMA
Request for details.
DMA0 transfer counter reload register TCR0 (16)
DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 transfer counter TCR1 (16)
Jan 10, 2006
DMAC Block Diagram
Page 126 of 390
(addresses 0029h, 0028h)
(addresses 0039h, 0038h)
Data bus high-order bits
Data bus low-order bits
Address bus
DMA latch high-order bits
DMA0 source pointer SAR0(20)
DMA0 destination pointer DAR0 (20)
DMA0 forward address pointer (20)
DMA1 source pointer SAR1 (20)
DMA1 destination pointer DAR1 (20)
DMA1 forward address pointer (20)
NOTES :
1. Pointer is incremented by a DMA request.
(addresses 0022h to 0020h)
(addresses 0032h to 0030h)
DMA latch low-order bits
(addresses 0026h to 0024h)
(addresses 0036h to 0034h)
(1)
(1)
14. DMAC