M30626FJPFP#D5C Renesas Electronics America, M30626FJPFP#D5C Datasheet - Page 224

• Manufacturer Part Number: M30626FJPFP#D5C
• Description: MCU 3/5V 512K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPFP#D5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Table 17.11
NOTES:
i=0 to 2
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
Register
1. Set the bit 4 and bit 5 in the U0C1 and U1C1 register to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are
2. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to “0”.
3. Not all register bits are described above. Set those bits to “0” when writing to the registers in I
4. When using UART1 in I
(3)
(3)
(3)
in the UCON register.
U1C0 register to “0” (CTS/RTS enable) and the CRS bit to “0” (CTS input).
Jan 10, 2006
0 to 7
0 to 7
8
ABT
OER
0 to 7
SMD2 to SMD0
CKDIR
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2RRM
UiLCH, UiERE
IICM
ABC
BBS
3 to 7
IICM2
CSC
SWC
ALS
STAC
SWC2
SDHI
7
Registers to Be Used and Settings in I
(4)
(1)
Bit
(1)
,
Page 207 of 390
2
C mode and enabling the CTS/RTS separate function of UART0, set the CRD bit in the
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Arbitration lost detection flag
Overrun error flag
Set a bit rate
Set to “010b”
Set to “0”
Set to “0”
Select the count source for the UiBRG
register
Invalid because CRD = 1
Transmit buffer empty flag
Set to “1”
Set to “1”
Set to “0”
Set to “1”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Invalid
Set to “0”
Set to “1”
Select the timing at which arbitration-lost
is detected
Bus busy flag
Set to “0”
See Table 17.13 I
Set this bit to “1” to enable clock
synchronization
Set this bit to “1” to have SCLi output fixed
to “L” at the falling edge of the 9th bit of
clock
Set this bit to “1” to have SDAi output
stopped when arbitration-lost is detected
Set to “0”
Set this bit to “1” to have SCLi output
forcibly pulled low
Set this bit to “1” to disable SDAi output
Set to “0”
(2)
Master
2
C Mode Functions
2
C Mode (1)
Function
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Invalid
Overrun error flag
Invalid
Set to “010b”
Set to “1”
Set to “0”
Invalid
Invalid because CRD = 1
Transmit buffer empty flag
Set to “1”
Set to “1”
Set to “0”
Set to “1”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Invalid
Set to “0”
Set to “1”
Invalid
Bus busy flag
Set to “0”
See Table 17.13 I
Set to “0”
Set this bit to “1” to have SCLi output fixed
to “L” at the falling edge of the 9th bit of
clock
Set to “0”
Set this bit to “1” to initialize UARTi at
start condition detection
Set this bit to “1” to have SCLi output
forcibly pulled low
Set this bit to “1” to disable SDAi output
Set to “0”
(2)
Slave
2
C Mode Functions
17. Serial Interface
2
C mode.