M30626FJPFP#D5C Renesas Electronics America, M30626FJPFP#D5C Datasheet - Page 229

• Manufacturer Part Number: M30626FJPFP#D5C
• Description: MCU 3/5V 512K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPFP#D5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.28
Table 17.14
Output of SCLi and SDAi Pins
Start/Stop Condition Interrupt
Request Generation Timing
17.1.3.3
Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising edge of
SCLi. Use the ABC bit in the UiSMR register to select the timing at which the ABT bit in the UiRB register is
updated. If the ABC bit = 0 (updated bitwise), the ABT bit is set to “1” at the same time unmatching is detected
during check, and is cleared to “0” when not detected. In cases when the ABC bit is set to “1”, if unmatching is
detected even once during check, the ABT bit is set to “1” (unmatching detected) at the falling edge of the clock
pulse of 9th bit. If the ABT bit needs to be updated bytewise, clear the ABT bit to “0” (undetected) after
detecting acknowledge in the first byte, before transferring the next byte.
Setting the ALS bit in the UiSMR2 register to “1” (SDA output stop enabled) factors arbitration-lost to occur, in
which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit is set to “1”
(unmatching detected).
STSPSEL bit
SCLi
SDAi
STSPSEL bit
SCLi
SDAi
(1) When Slave
(2) When Master
Jan 10, 2006
CKDIR=1 (external clock)
CKDIR=0 (internal clock), CKPH=1 (clock delayed)
Function
STSPSEL Bit Functions
STSPSEL Bit Functions
Arbitration
Set STAREQ=1
(start)
0
Set to “1” in
a program
Page 212 of 390
Start condition
detection interrupt
Output of transfer clock and data
Output of start/stop condition is
accomplished by a program using
ports (not automatically generated
in hardware)
Start/stop condition detection
Start condition detection
interrupt
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
Set to “0” in
a program
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
STSPSEL = 0
Set STPREQ=1
(start)
Stop condition
detection interrupt
Output of a start/stop condition
according to the STAREQ,
RSTAREQ and STPREQ bit
Finish generating start/stop
condition
Set to “1” in
a program
Stop condition detection
interrupt
STSPSEL = 1
Set to “0” in
a program
17. Serial Interface