M30626FJPFP#D5C Renesas Electronics America, M30626FJPFP#D5C Datasheet - Page 243

MCU 3/5V 512K 100-QFP

M30626FJPFP#D5C

Manufacturer Part Number
M30626FJPFP#D5C
Description
MCU 3/5V 512K 100-QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheet

Specifications of M30626FJPFP#D5C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.37
17.1.6.2
When direct format, set the PRYE bit in the U2MR register to “1”, the PRY bit to “1”, the UFORM bit in the
U2C0 register to “0” and the U2LCH bit in the U2C1 register to “0”. When data are transmitted, data set in the
U2TB register are transmitted with the even-numbered parity, starting from D0. When data are received,
received data are stored in the U2RB register, starting from D0. The even-numbered parity determines whether
a parity error occurs.
When inverse format, set the PRYE bit to “1”, the PRY bit to “0”, the UFORM bit to “1” and the U2LCH bit to
“1”. When data are transmitted, values set in the U2TB register are logically inversed and are transmitted with
the odd-numbered parity, starting from D7. When data are received, received data are logically inversed to be
stored in the U2RB register, starting from D7. The odd-numbered parity determines whether a parity error
occurs.
Jan 10, 2006
(1) Direct format
(2) Inverse format
Transfer
Transfer
Format
SIM Interface Format
TXD2
TXD2
clcck
clcck
“H”
“H”
“H”
“H”
“L”
“L”
“L”
“L”
Page 226 of 390
D0
D7
D6
D1
D5
D2
D4
D3
D3
D4
D2
D5
D1
D6
D0
D7
P
P
P : Even parity
P : Odd parity
17. Serial Interface

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