M30626FJPFP#D5C Renesas Electronics America, M30626FJPFP#D5C Datasheet - Page 245

• Manufacturer Part Number: M30626FJPFP#D5C
• Description: MCU 3/5V 512K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPFP#D5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.39
SI/Oi Control Register (i=3, 4)
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1.
2.
3.
4.
5.
6. When changing the SMi1 to SMi0 bits, set the SiBRG register.
Make sure this register is w ritten to by the next instruction after setting the PRC2 bit in the PRCR register to “1” (w rite
enable).
Set the SMi3 bit to “1” and the corresponding port direction bit to “0” (input mode).
Set the SMi3 bit to “1” (SOUTi output, CLKi function).
When the SMi2 bit is set to “1,” the target pin goes to a high-impedance state regardless of w hich function of the pin is
being used.
Selected by PCLK1 bit in the PCLKR register.
Jan 10, 2006
SiC Register
Bit Symbol
SMi0
SMi1
SMi2
SMi3
SMi4
SMi5
SMi6
SMi7
Page 228 of 390
Symbol
S3C
S4C
(1)
Internal Synchronous
Clock Select Bit
SOUTi Output Disable Bit
S I/Oi Port Select Bit
CLK Polarity Select Bit
Transfer Direction Select Bit
Synchronous Clock
Select Bit
SOUTi Initial Value Set Bit
Bit Name
(6)
Address
0362h
0366h
(4)
b1 b0
0 0 : Selecting f1SIO or f2SIO
0 1 : Selecting f8SIO
1 0 : Selecting f32SIO
1 1 : Do not set to this value
0 : SOUTi output
1 : SOUTi output disable (High-Impedance)
0 : Input/output port
1 : SOUTi output, CLKi function
0 : Transmit data is output at falling edge of transfer
1 : Transmit data is output at rising edge of transfer
0 : LSB first
1 : MSB first
0 : External clock
1 : Internal clock
Effective w hen SMi3 = 0
0 : “L” output
1 : “H” output
clock and receive data is input at rising edge
clock and receive data is input at falling edge
(3)
(2)
After Reset
01000000b
01000000b
Function
(5)
17. Serial Interface
RW
RW
RW
RW
RW
RW
RW
RW
RW