M30626FJPFP#D5C Renesas Electronics America, M30626FJPFP#D5C Datasheet - Page 270

• Manufacturer Part Number: M30626FJPFP#D5C
• Description: MCU 3/5V 512K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPFP#D5C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
20. CRC Calculation
The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a generator
polynomial of CRC_CCITT (X
The CRC code consists of 16 bits which are generated for each data block in given length, separated in 8 bit units.
After the initial value is set in the CRCD register, the CRC code is set in that register each time one byte of data is
written to the CRCIN register. CRC code generation for one-byte data is finished in two cycles.
Figure 20.1 shows the CRC Circuit Block Diagram. Figure 20.2 shows the CRC-related Registers.
Figure 20.3 shows the Calculation Example using the CRC Operation.
Figure 20.1
Figure 20.2
CRC Data Register
CRC Input Register
(b15)
b7
b7
Jan 10, 2006
CRCD and CRCIN Registers
CRC Circuit Block Diagram
(b8)
b0
b0
b7
When data is w ritten to the CRCIN register after setting the initial value in
the CRCD register, the CRC code can be read out from the CRCD
register.
Data input
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16
+ X
CRCIN register
12
b0
+ X
CRC code generating circuit
5
Eight low-order bits
+ 1) to generate CRC code.
Data bus high-order
Data bus low-order
Symbol
CRCD
Symbol
CRCIN
CRCD register
X
16
Function
Function
+ X
12
+ X
5
+ 1
03BDh to 03BCh
Address
Address
03BEh
Eight high-order bits
0000h to FFFFh
Setting Range
Setting Range
Indeterminate
Indeterminate
After Reset
After Reset
00h to FFh
20. CRC Calculation
RW
RW
RW
RW